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openpilot v0.9.6 release

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date: 2024-02-21T23:02:42
master commit: 0b4d08fab8e35a264bc7383e878538f8083c33e5
This commit is contained in:
FrogAi
2024-02-27 16:34:45 -07:00
commit 2901597132
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78
third_party/linux/include/linux/ion.h vendored Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _UAPI_LINUX_ION_H
#define _UAPI_LINUX_ION_H
#include <linux/ioctl.h>
#include <linux/types.h>
typedef int ion_user_handle_t;
enum ion_heap_type {
ION_HEAP_TYPE_SYSTEM,
ION_HEAP_TYPE_SYSTEM_CONTIG,
ION_HEAP_TYPE_CARVEOUT,
ION_HEAP_TYPE_CHUNK,
ION_HEAP_TYPE_DMA,
ION_HEAP_TYPE_CUSTOM,
};
#define ION_NUM_HEAP_IDS (sizeof(unsigned int) * 8)
#define ION_FLAG_CACHED 1
#define ION_FLAG_CACHED_NEEDS_SYNC 2
struct ion_allocation_data {
size_t len;
size_t align;
unsigned int heap_id_mask;
unsigned int flags;
ion_user_handle_t handle;
};
struct ion_fd_data {
ion_user_handle_t handle;
int fd;
};
struct ion_handle_data {
ion_user_handle_t handle;
};
struct ion_custom_data {
unsigned int cmd;
unsigned long arg;
};
#define MAX_HEAP_NAME 32
struct ion_heap_data {
char name[MAX_HEAP_NAME];
__u32 type;
__u32 heap_id;
__u32 reserved0;
__u32 reserved1;
__u32 reserved2;
};
struct ion_heap_query {
__u32 cnt;
__u32 reserved0;
__u64 heaps;
__u32 reserved1;
__u32 reserved2;
};
#define ION_IOC_MAGIC 'I'
#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, struct ion_allocation_data)
#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data)
#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data)
#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data)
#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)
#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)
#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
#define ION_IOC_HEAP_QUERY _IOWR(ION_IOC_MAGIC, 8, struct ion_heap_query)
#endif

25
third_party/linux/include/media/cam_cpas.h vendored Normal file
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#ifndef __UAPI_CAM_CPAS_H__
#define __UAPI_CAM_CPAS_H__
#include "cam_defs.h"
#define CAM_FAMILY_CAMERA_SS 1
#define CAM_FAMILY_CPAS_SS 2
/**
* struct cam_cpas_query_cap - CPAS query device capability payload
*
* @camera_family : Camera family type
* @reserved : Reserved field for alignment
* @camera_version : Camera platform version
* @cpas_version : Camera CPAS version within camera platform
*
*/
struct cam_cpas_query_cap {
uint32_t camera_family;
uint32_t reserved;
struct cam_hw_version camera_version;
struct cam_hw_version cpas_version;
};
#endif /* __UAPI_CAM_CPAS_H__ */

477
third_party/linux/include/media/cam_defs.h vendored Normal file
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#ifndef __UAPI_CAM_DEFS_H__
#define __UAPI_CAM_DEFS_H__
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
/* camera op codes */
#define CAM_COMMON_OPCODE_BASE 0x100
#define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1)
#define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2)
#define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3)
#define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4)
#define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5)
#define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6)
#define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7)
#define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8)
#define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9)
#define CAM_EXT_OPCODE_BASE 0x200
#define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1)
/* camera handle type */
#define CAM_HANDLE_USER_POINTER 1
#define CAM_HANDLE_MEM_HANDLE 2
/* Generic Blob CmdBuffer header properties */
#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00
#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8
#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF
#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0
/* Command Buffer Types */
#define CAM_CMD_BUF_DMI 0x1
#define CAM_CMD_BUF_DMI16 0x2
#define CAM_CMD_BUF_DMI32 0x3
#define CAM_CMD_BUF_DMI64 0x4
#define CAM_CMD_BUF_DIRECT 0x5
#define CAM_CMD_BUF_INDIRECT 0x6
#define CAM_CMD_BUF_I2C 0x7
#define CAM_CMD_BUF_FW 0x8
#define CAM_CMD_BUF_GENERIC 0x9
#define CAM_CMD_BUF_LEGACY 0xA
/**
* enum flush_type_t - Identifies the various flush types
*
* @CAM_FLUSH_TYPE_REQ: Flush specific request
* @CAM_FLUSH_TYPE_ALL: Flush all requests belonging to a context
* @CAM_FLUSH_TYPE_MAX: Max enum to validate flush type
*
*/
enum flush_type_t {
CAM_FLUSH_TYPE_REQ,
CAM_FLUSH_TYPE_ALL,
CAM_FLUSH_TYPE_MAX
};
/**
* struct cam_control - Structure used by ioctl control for camera
*
* @op_code: This is the op code for camera control
* @size: Control command size
* @handle_type: User pointer or shared memory handle
* @reserved: Reserved field for 64 bit alignment
* @handle: Control command payload
*/
struct cam_control {
uint32_t op_code;
uint32_t size;
uint32_t handle_type;
uint32_t reserved;
uint64_t handle;
};
/* camera IOCTL */
#define VIDIOC_CAM_CONTROL \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control)
/**
* struct cam_hw_version - Structure for HW version of camera devices
*
* @major : Hardware version major
* @minor : Hardware version minor
* @incr : Hardware version increment
* @reserved : Reserved for 64 bit aligngment
*/
struct cam_hw_version {
uint32_t major;
uint32_t minor;
uint32_t incr;
uint32_t reserved;
};
/**
* struct cam_iommu_handle - Structure for IOMMU handles of camera hw devices
*
* @non_secure: Device Non Secure IOMMU handle
* @secure: Device Secure IOMMU handle
*
*/
struct cam_iommu_handle {
int32_t non_secure;
int32_t secure;
};
/* camera secure mode */
#define CAM_SECURE_MODE_NON_SECURE 0
#define CAM_SECURE_MODE_SECURE 1
/* Camera Format Type */
#define CAM_FORMAT_BASE 0
#define CAM_FORMAT_MIPI_RAW_6 1
#define CAM_FORMAT_MIPI_RAW_8 2
#define CAM_FORMAT_MIPI_RAW_10 3
#define CAM_FORMAT_MIPI_RAW_12 4
#define CAM_FORMAT_MIPI_RAW_14 5
#define CAM_FORMAT_MIPI_RAW_16 6
#define CAM_FORMAT_MIPI_RAW_20 7
#define CAM_FORMAT_QTI_RAW_8 8
#define CAM_FORMAT_QTI_RAW_10 9
#define CAM_FORMAT_QTI_RAW_12 10
#define CAM_FORMAT_QTI_RAW_14 11
#define CAM_FORMAT_PLAIN8 12
#define CAM_FORMAT_PLAIN16_8 13
#define CAM_FORMAT_PLAIN16_10 14
#define CAM_FORMAT_PLAIN16_12 15
#define CAM_FORMAT_PLAIN16_14 16
#define CAM_FORMAT_PLAIN16_16 17
#define CAM_FORMAT_PLAIN32_20 18
#define CAM_FORMAT_PLAIN64 19
#define CAM_FORMAT_PLAIN128 20
#define CAM_FORMAT_ARGB 21
#define CAM_FORMAT_ARGB_10 22
#define CAM_FORMAT_ARGB_12 23
#define CAM_FORMAT_ARGB_14 24
#define CAM_FORMAT_DPCM_10_6_10 25
#define CAM_FORMAT_DPCM_10_8_10 26
#define CAM_FORMAT_DPCM_12_6_12 27
#define CAM_FORMAT_DPCM_12_8_12 28
#define CAM_FORMAT_DPCM_14_8_14 29
#define CAM_FORMAT_DPCM_14_10_14 30
#define CAM_FORMAT_NV21 31
#define CAM_FORMAT_NV12 32
#define CAM_FORMAT_TP10 33
#define CAM_FORMAT_YUV422 34
#define CAM_FORMAT_PD8 35
#define CAM_FORMAT_PD10 36
#define CAM_FORMAT_UBWC_NV12 37
#define CAM_FORMAT_UBWC_NV12_4R 38
#define CAM_FORMAT_UBWC_TP10 39
#define CAM_FORMAT_UBWC_P010 40
#define CAM_FORMAT_PLAIN8_SWAP 41
#define CAM_FORMAT_PLAIN8_10 42
#define CAM_FORMAT_PLAIN8_10_SWAP 43
#define CAM_FORMAT_YV12 44
#define CAM_FORMAT_Y_ONLY 45
#define CAM_FORMAT_MAX 46
/* camera rotaion */
#define CAM_ROTATE_CW_0_DEGREE 0
#define CAM_ROTATE_CW_90_DEGREE 1
#define CAM_RORATE_CW_180_DEGREE 2
#define CAM_ROTATE_CW_270_DEGREE 3
/* camera Color Space */
#define CAM_COLOR_SPACE_BASE 0
#define CAM_COLOR_SPACE_BT601_FULL 1
#define CAM_COLOR_SPACE_BT601625 2
#define CAM_COLOR_SPACE_BT601525 3
#define CAM_COLOR_SPACE_BT709 4
#define CAM_COLOR_SPACE_DEPTH 5
#define CAM_COLOR_SPACE_MAX 6
/* camera buffer direction */
#define CAM_BUF_INPUT 1
#define CAM_BUF_OUTPUT 2
#define CAM_BUF_IN_OUT 3
/* camera packet device Type */
#define CAM_PACKET_DEV_BASE 0
#define CAM_PACKET_DEV_IMG_SENSOR 1
#define CAM_PACKET_DEV_ACTUATOR 2
#define CAM_PACKET_DEV_COMPANION 3
#define CAM_PACKET_DEV_EEPOM 4
#define CAM_PACKET_DEV_CSIPHY 5
#define CAM_PACKET_DEV_OIS 6
#define CAM_PACKET_DEV_FLASH 7
#define CAM_PACKET_DEV_FD 8
#define CAM_PACKET_DEV_JPEG_ENC 9
#define CAM_PACKET_DEV_JPEG_DEC 10
#define CAM_PACKET_DEV_VFE 11
#define CAM_PACKET_DEV_CPP 12
#define CAM_PACKET_DEV_CSID 13
#define CAM_PACKET_DEV_ISPIF 14
#define CAM_PACKET_DEV_IFE 15
#define CAM_PACKET_DEV_ICP 16
#define CAM_PACKET_DEV_LRME 17
#define CAM_PACKET_DEV_MAX 18
/* constants */
#define CAM_PACKET_MAX_PLANES 3
/**
* struct cam_plane_cfg - Plane configuration info
*
* @width: Plane width in pixels
* @height: Plane height in lines
* @plane_stride: Plane stride in pixel
* @slice_height: Slice height in line (not used by ISP)
* @meta_stride: UBWC metadata stride
* @meta_size: UBWC metadata plane size
* @meta_offset: UBWC metadata offset
* @packer_config: UBWC packer config
* @mode_config: UBWC mode config
* @tile_config: UBWC tile config
* @h_init: UBWC horizontal initial coordinate in pixels
* @v_init: UBWC vertical initial coordinate in lines
*
*/
struct cam_plane_cfg {
uint32_t width;
uint32_t height;
uint32_t plane_stride;
uint32_t slice_height;
uint32_t meta_stride;
uint32_t meta_size;
uint32_t meta_offset;
uint32_t packer_config;
uint32_t mode_config;
uint32_t tile_config;
uint32_t h_init;
uint32_t v_init;
};
/**
* struct cam_cmd_buf_desc - Command buffer descriptor
*
* @mem_handle: Command buffer handle
* @offset: Command start offset
* @size: Size of the command buffer in bytes
* @length: Used memory in command buffer in bytes
* @type: Type of the command buffer
* @meta_data: Data type for private command buffer
* Between UMD and KMD
*
*/
struct cam_cmd_buf_desc {
int32_t mem_handle;
uint32_t offset;
uint32_t size;
uint32_t length;
uint32_t type;
uint32_t meta_data;
};
/**
* struct cam_buf_io_cfg - Buffer io configuration for buffers
*
* @mem_handle: Mem_handle array for the buffers.
* @offsets: Offsets for each planes in the buffer
* @planes: Per plane information
* @width: Main plane width in pixel
* @height: Main plane height in lines
* @format: Format of the buffer
* @color_space: Color space for the buffer
* @color_pattern: Color pattern in the buffer
* @bpp: Bit per pixel
* @rotation: Rotation information for the buffer
* @resource_type: Resource type associated with the buffer
* @fence: Fence handle
* @early_fence: Fence handle for early signal
* @aux_cmd_buf: An auxiliary command buffer that may be
* used for programming the IO
* @direction: Direction of the config
* @batch_size: Batch size in HFR mode
* @subsample_pattern: Subsample pattern. Used in HFR mode. It
* should be consistent with batchSize and
* CAMIF programming.
* @subsample_period: Subsample period. Used in HFR mode. It
* should be consistent with batchSize and
* CAMIF programming.
* @framedrop_pattern: Framedrop pattern
* @framedrop_period: Framedrop period
* @flag: Flags for extra information
* @direction: Buffer direction: input or output
* @padding: Padding for the structure
*
*/
struct cam_buf_io_cfg {
int32_t mem_handle[CAM_PACKET_MAX_PLANES];
uint32_t offsets[CAM_PACKET_MAX_PLANES];
struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES];
uint32_t format;
uint32_t color_space;
uint32_t color_pattern;
uint32_t bpp;
uint32_t rotation;
uint32_t resource_type;
int32_t fence;
int32_t early_fence;
struct cam_cmd_buf_desc aux_cmd_buf;
uint32_t direction;
uint32_t batch_size;
uint32_t subsample_pattern;
uint32_t subsample_period;
uint32_t framedrop_pattern;
uint32_t framedrop_period;
uint32_t flag;
uint32_t padding;
};
/**
* struct cam_packet_header - Camera packet header
*
* @op_code: Camera packet opcode
* @size: Size of the camera packet in bytes
* @request_id: Request id for this camera packet
* @flags: Flags for the camera packet
* @padding: Padding
*
*/
struct cam_packet_header {
uint32_t op_code;
uint32_t size;
uint64_t request_id;
uint32_t flags;
uint32_t padding;
};
/**
* struct cam_patch_desc - Patch structure
*
* @dst_buf_hdl: Memory handle for the dest buffer
* @dst_offset: Offset byte in the dest buffer
* @src_buf_hdl: Memory handle for the source buffer
* @src_offset: Offset byte in the source buffer
*
*/
struct cam_patch_desc {
int32_t dst_buf_hdl;
uint32_t dst_offset;
int32_t src_buf_hdl;
uint32_t src_offset;
};
/**
* struct cam_packet - Camera packet structure
*
* @header: Camera packet header
* @cmd_buf_offset: Command buffer start offset
* @num_cmd_buf: Number of the command buffer in the packet
* @io_config_offset: Buffer io configuration start offset
* @num_io_configs: Number of the buffer io configurations
* @patch_offset: Patch offset for the patch structure
* @num_patches: Number of the patch structure
* @kmd_cmd_buf_index: Command buffer index which contains extra
* space for the KMD buffer
* @kmd_cmd_buf_offset: Offset from the beginning of the command
* buffer for KMD usage.
* @payload: Camera packet payload
*
*/
struct cam_packet {
struct cam_packet_header header;
uint32_t cmd_buf_offset;
uint32_t num_cmd_buf;
uint32_t io_configs_offset;
uint32_t num_io_configs;
uint32_t patch_offset;
uint32_t num_patches;
uint32_t kmd_cmd_buf_index;
uint32_t kmd_cmd_buf_offset;
uint64_t payload[1];
};
/**
* struct cam_release_dev_cmd - Control payload for release devices
*
* @session_handle: Session handle for the release
* @dev_handle: Device handle for the release
*/
struct cam_release_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
};
/**
* struct cam_start_stop_dev_cmd - Control payload for start/stop device
*
* @session_handle: Session handle for the start/stop command
* @dev_handle: Device handle for the start/stop command
*
*/
struct cam_start_stop_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
};
/**
* struct cam_config_dev_cmd - Command payload for configure device
*
* @session_handle: Session handle for the command
* @dev_handle: Device handle for the command
* @offset: Offset byte in the packet handle.
* @packet_handle: Packet memory handle for the actual packet:
* struct cam_packet.
*
*/
struct cam_config_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
uint64_t offset;
uint64_t packet_handle;
};
/**
* struct cam_query_cap_cmd - Payload for query device capability
*
* @size: Handle size
* @handle_type: User pointer or shared memory handle
* @caps_handle: Device specific query command payload
*
*/
struct cam_query_cap_cmd {
uint32_t size;
uint32_t handle_type;
uint64_t caps_handle;
};
/**
* struct cam_acquire_dev_cmd - Control payload for acquire devices
*
* @session_handle: Session handle for the acquire command
* @dev_handle: Device handle to be returned
* @handle_type: Resource handle type:
* 1 = user pointer, 2 = mem handle
* @num_resources: Number of the resources to be acquired
* @resources_hdl: Resource handle that refers to the actual
* resource array. Each item in this
* array is device specific resource structure
*
*/
struct cam_acquire_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
uint32_t handle_type;
uint32_t num_resources;
uint64_t resource_hdl;
};
/**
* struct cam_flush_dev_cmd - Control payload for flush devices
*
* @version: Version
* @session_handle: Session handle for the acquire command
* @dev_handle: Device handle to be returned
* @flush_type: Flush type:
* 0 = flush specific request
* 1 = flush all
* @reserved: Reserved for 64 bit aligngment
* @req_id: Request id that needs to cancel
*
*/
struct cam_flush_dev_cmd {
uint64_t version;
int32_t session_handle;
int32_t dev_handle;
uint32_t flush_type;
uint32_t reserved;
int64_t req_id;
};
#endif /* __UAPI_CAM_DEFS_H__ */

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third_party/linux/include/media/cam_fd.h vendored Normal file
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#ifndef __UAPI_CAM_FD_H__
#define __UAPI_CAM_FD_H__
#include "cam_defs.h"
#define CAM_FD_MAX_FACES 35
#define CAM_FD_RAW_RESULT_ENTRIES 512
/* FD Op Codes */
#define CAM_PACKET_OPCODES_FD_FRAME_UPDATE 0x0
/* FD Command Buffer identifiers */
#define CAM_FD_CMD_BUFFER_ID_GENERIC 0x0
#define CAM_FD_CMD_BUFFER_ID_CDM 0x1
#define CAM_FD_CMD_BUFFER_ID_MAX 0x2
/* FD Blob types */
#define CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST 0x0
#define CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED 0x1
/* FD Resource IDs */
#define CAM_FD_INPUT_PORT_ID_IMAGE 0x0
#define CAM_FD_INPUT_PORT_ID_MAX 0x1
#define CAM_FD_OUTPUT_PORT_ID_RESULTS 0x0
#define CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS 0x1
#define CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER 0x2
#define CAM_FD_OUTPUT_PORT_ID_MAX 0x3
/**
* struct cam_fd_soc_clock_bw_request - SOC clock, bandwidth request info
*
* @clock_rate : Clock rate required while processing frame
* @bandwidth : Bandwidth required while processing frame
* @reserved : Reserved for future use
*/
struct cam_fd_soc_clock_bw_request {
uint64_t clock_rate;
uint64_t bandwidth;
uint64_t reserved[4];
};
/**
* struct cam_fd_face - Face properties
*
* @prop1 : Property 1 of face
* @prop2 : Property 2 of face
* @prop3 : Property 3 of face
* @prop4 : Property 4 of face
*
* Do not change this layout, this is inline with how HW writes
* these values directly when the buffer is programmed to HW
*/
struct cam_fd_face {
uint32_t prop1;
uint32_t prop2;
uint32_t prop3;
uint32_t prop4;
};
/**
* struct cam_fd_results - FD results layout
*
* @faces : Array of faces with face properties
* @face_count : Number of faces detected
* @reserved : Reserved for alignment
*
* Do not change this layout, this is inline with how HW writes
* these values directly when the buffer is programmed to HW
*/
struct cam_fd_results {
struct cam_fd_face faces[CAM_FD_MAX_FACES];
uint32_t face_count;
uint32_t reserved[3];
};
/**
* struct cam_fd_hw_caps - Face properties
*
* @core_version : FD core version
* @wrapper_version : FD wrapper version
* @raw_results_available : Whether raw results are available on this HW
* @supported_modes : Modes supported by this HW.
* @reserved : Reserved for future use
*/
struct cam_fd_hw_caps {
struct cam_hw_version core_version;
struct cam_hw_version wrapper_version;
uint32_t raw_results_available;
uint32_t supported_modes;
uint64_t reserved;
};
/**
* struct cam_fd_query_cap_cmd - FD Query capabilities information
*
* @device_iommu : FD IOMMU handles
* @cdm_iommu : CDM iommu handles
* @hw_caps : FD HW capabilities
* @reserved : Reserved for alignment
*/
struct cam_fd_query_cap_cmd {
struct cam_iommu_handle device_iommu;
struct cam_iommu_handle cdm_iommu;
struct cam_fd_hw_caps hw_caps;
uint64_t reserved;
};
/**
* struct cam_fd_acquire_dev_info - FD acquire device information
*
* @clk_bw_request : SOC clock, bandwidth request
* @priority : Priority for this acquire
* @mode : Mode in which to run FD HW.
* @get_raw_results : Whether this acquire needs face raw results
* while frame processing
* @reserved : Reserved field for 64 bit alignment
*/
struct cam_fd_acquire_dev_info {
struct cam_fd_soc_clock_bw_request clk_bw_request;
uint32_t priority;
uint32_t mode;
uint32_t get_raw_results;
uint32_t reserved[13];
};
#endif /* __UAPI_CAM_FD_H__ */

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third_party/linux/include/media/cam_icp.h vendored Normal file
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#ifndef __UAPI_CAM_ICP_H__
#define __UAPI_CAM_ICP_H__
#include "cam_defs.h"
/* icp, ipe, bps, cdm(ipe/bps) are used in querycap */
#define CAM_ICP_DEV_TYPE_A5 1
#define CAM_ICP_DEV_TYPE_IPE 2
#define CAM_ICP_DEV_TYPE_BPS 3
#define CAM_ICP_DEV_TYPE_IPE_CDM 4
#define CAM_ICP_DEV_TYPE_BPS_CDM 5
#define CAM_ICP_DEV_TYPE_MAX 5
/* definitions needed for icp aquire device */
#define CAM_ICP_RES_TYPE_BPS 1
#define CAM_ICP_RES_TYPE_IPE_RT 2
#define CAM_ICP_RES_TYPE_IPE 3
#define CAM_ICP_RES_TYPE_MAX 4
/* packet opcode types */
#define CAM_ICP_OPCODE_IPE_UPDATE 0
#define CAM_ICP_OPCODE_BPS_UPDATE 1
/* IPE input port resource type */
#define CAM_ICP_IPE_INPUT_IMAGE_FULL 0x0
#define CAM_ICP_IPE_INPUT_IMAGE_DS4 0x1
#define CAM_ICP_IPE_INPUT_IMAGE_DS16 0x2
#define CAM_ICP_IPE_INPUT_IMAGE_DS64 0x3
#define CAM_ICP_IPE_INPUT_IMAGE_FULL_REF 0x4
#define CAM_ICP_IPE_INPUT_IMAGE_DS4_REF 0x5
#define CAM_ICP_IPE_INPUT_IMAGE_DS16_REF 0x6
#define CAM_ICP_IPE_INPUT_IMAGE_DS64_REF 0x7
/* IPE output port resource type */
#define CAM_ICP_IPE_OUTPUT_IMAGE_DISPLAY 0x8
#define CAM_ICP_IPE_OUTPUT_IMAGE_VIDEO 0x9
#define CAM_ICP_IPE_OUTPUT_IMAGE_FULL_REF 0xA
#define CAM_ICP_IPE_OUTPUT_IMAGE_DS4_REF 0xB
#define CAM_ICP_IPE_OUTPUT_IMAGE_DS16_REF 0xC
#define CAM_ICP_IPE_OUTPUT_IMAGE_DS64_REF 0xD
#define CAM_ICP_IPE_IMAGE_MAX 0xE
/* BPS input port resource type */
#define CAM_ICP_BPS_INPUT_IMAGE 0x0
/* BPS output port resource type */
#define CAM_ICP_BPS_OUTPUT_IMAGE_FULL 0x1
#define CAM_ICP_BPS_OUTPUT_IMAGE_DS4 0x2
#define CAM_ICP_BPS_OUTPUT_IMAGE_DS16 0x3
#define CAM_ICP_BPS_OUTPUT_IMAGE_DS64 0x4
#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BG 0x5
#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BHIST 0x6
#define CAM_ICP_BPS_OUTPUT_IMAGE_REG1 0x7
#define CAM_ICP_BPS_OUTPUT_IMAGE_REG2 0x8
#define CAM_ICP_BPS_IO_IMAGES_MAX 0x9
/* Command meta types */
#define CAM_ICP_CMD_META_GENERIC_BLOB 0x1
/* Generic blob types */
#define CAM_ICP_CMD_GENERIC_BLOB_CLK 0x1
#define CAM_ICP_CMD_GENERIC_BLOB_CFG_IO 0x2
/**
* struct cam_icp_clk_bw_request
*
* @budget_ns: Time required to process frame
* @frame_cycles: Frame cycles needed to process the frame
* @rt_flag: Flag to indicate real time stream
* @uncompressed_bw: Bandwidth required to process frame
* @compressed_bw: Compressed bandwidth to process frame
*/
struct cam_icp_clk_bw_request {
uint64_t budget_ns;
uint32_t frame_cycles;
uint32_t rt_flag;
uint64_t uncompressed_bw;
uint64_t compressed_bw;
};
/**
* struct cam_icp_dev_ver - Device information for particular hw type
*
* This is used to get device version info of
* ICP, IPE, BPS and CDM related IPE and BPS from firmware
* and use this info in CAM_QUERY_CAP IOCTL
*
* @dev_type: hardware type for the cap info(icp, ipe, bps, cdm(ipe/bps))
* @reserved: reserved field
* @hw_ver: major, minor and incr values of a device version
*/
struct cam_icp_dev_ver {
uint32_t dev_type;
uint32_t reserved;
struct cam_hw_version hw_ver;
};
/**
* struct cam_icp_ver - ICP version info
*
* This strcuture is used for fw and api version
* this is used to get firmware version and api version from firmware
* and use this info in CAM_QUERY_CAP IOCTL
*
* @major: FW version major
* @minor: FW version minor
* @revision: FW version increment
*/
struct cam_icp_ver {
uint32_t major;
uint32_t minor;
uint32_t revision;
uint32_t reserved;
};
/**
* struct cam_icp_query_cap_cmd - ICP query device capability payload
*
* @dev_iommu_handle: icp iommu handles for secure/non secure modes
* @cdm_iommu_handle: iommu handles for secure/non secure modes
* @fw_version: firmware version info
* @api_version: api version info
* @num_ipe: number of ipes
* @num_bps: number of bps
* @dev_ver: returned device capability array
*/
struct cam_icp_query_cap_cmd {
struct cam_iommu_handle dev_iommu_handle;
struct cam_iommu_handle cdm_iommu_handle;
struct cam_icp_ver fw_version;
struct cam_icp_ver api_version;
uint32_t num_ipe;
uint32_t num_bps;
struct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX];
};
/**
* struct cam_icp_res_info - ICP output resource info
*
* @format: format of the resource
* @width: width in pixels
* @height: height in lines
* @fps: fps
*/
struct cam_icp_res_info {
uint32_t format;
uint32_t width;
uint32_t height;
uint32_t fps;
};
/**
* struct cam_icp_acquire_dev_info - An ICP device info
*
* @scratch_mem_size: Output param - size of scratch memory
* @dev_type: device type (IPE_RT/IPE_NON_RT/BPS)
* @io_config_cmd_size: size of IO config command
* @io_config_cmd_handle: IO config command for each acquire
* @secure_mode: camera mode (secure/non secure)
* @chain_info: chaining info of FW device handles
* @in_res: resource info used for clock and bandwidth calculation
* @num_out_res: number of output resources
* @out_res: output resource
*/
struct cam_icp_acquire_dev_info {
uint32_t scratch_mem_size;
uint32_t dev_type;
uint32_t io_config_cmd_size;
int32_t io_config_cmd_handle;
uint32_t secure_mode;
int32_t chain_info;
struct cam_icp_res_info in_res;
uint32_t num_out_res;
struct cam_icp_res_info out_res[1];
} __attribute__((__packed__));
#endif /* __UAPI_CAM_ICP_H__ */

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#ifndef __UAPI_CAM_ISP_H__
#define __UAPI_CAM_ISP_H__
#include "cam_defs.h"
#include "cam_isp_vfe.h"
#include "cam_isp_ife.h"
/* ISP driver name */
#define CAM_ISP_DEV_NAME "cam-isp"
/* HW type */
#define CAM_ISP_HW_BASE 0
#define CAM_ISP_HW_CSID 1
#define CAM_ISP_HW_VFE 2
#define CAM_ISP_HW_IFE 3
#define CAM_ISP_HW_ISPIF 4
#define CAM_ISP_HW_MAX 5
/* Color Pattern */
#define CAM_ISP_PATTERN_BAYER_RGRGRG 0
#define CAM_ISP_PATTERN_BAYER_GRGRGR 1
#define CAM_ISP_PATTERN_BAYER_BGBGBG 2
#define CAM_ISP_PATTERN_BAYER_GBGBGB 3
#define CAM_ISP_PATTERN_YUV_YCBYCR 4
#define CAM_ISP_PATTERN_YUV_YCRYCB 5
#define CAM_ISP_PATTERN_YUV_CBYCRY 6
#define CAM_ISP_PATTERN_YUV_CRYCBY 7
#define CAM_ISP_PATTERN_MAX 8
/* Usage Type */
#define CAM_ISP_RES_USAGE_SINGLE 0
#define CAM_ISP_RES_USAGE_DUAL 1
#define CAM_ISP_RES_USAGE_MAX 2
/* Resource ID */
#define CAM_ISP_RES_ID_PORT 0
#define CAM_ISP_RES_ID_CLK 1
#define CAM_ISP_RES_ID_MAX 2
/* Resource Type - Type of resource for the resource id
* defined in cam_isp_vfe.h, cam_isp_ife.h
*/
/* Lane Type in input resource for Port */
#define CAM_ISP_LANE_TYPE_DPHY 0
#define CAM_ISP_LANE_TYPE_CPHY 1
#define CAM_ISP_LANE_TYPE_MAX 2
/* ISP Resurce Composite Group ID */
#define CAM_ISP_RES_COMP_GROUP_NONE 0
#define CAM_ISP_RES_COMP_GROUP_ID_0 1
#define CAM_ISP_RES_COMP_GROUP_ID_1 2
#define CAM_ISP_RES_COMP_GROUP_ID_2 3
#define CAM_ISP_RES_COMP_GROUP_ID_3 4
#define CAM_ISP_RES_COMP_GROUP_ID_4 5
#define CAM_ISP_RES_COMP_GROUP_ID_5 6
#define CAM_ISP_RES_COMP_GROUP_ID_MAX 6
/* ISP packet opcode for ISP */
#define CAM_ISP_PACKET_OP_BASE 0
#define CAM_ISP_PACKET_INIT_DEV 1
#define CAM_ISP_PACKET_UPDATE_DEV 2
#define CAM_ISP_PACKET_OP_MAX 3
/* ISP packet meta_data type for command buffer */
#define CAM_ISP_PACKET_META_BASE 0
#define CAM_ISP_PACKET_META_LEFT 1
#define CAM_ISP_PACKET_META_RIGHT 2
#define CAM_ISP_PACKET_META_COMMON 3
#define CAM_ISP_PACKET_META_DMI_LEFT 4
#define CAM_ISP_PACKET_META_DMI_RIGHT 5
#define CAM_ISP_PACKET_META_DMI_COMMON 6
#define CAM_ISP_PACKET_META_CLOCK 7
#define CAM_ISP_PACKET_META_CSID 8
#define CAM_ISP_PACKET_META_DUAL_CONFIG 9
#define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10
#define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11
#define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12
/* DSP mode */
#define CAM_ISP_DSP_MODE_NONE 0
#define CAM_ISP_DSP_MODE_ONE_WAY 1
#define CAM_ISP_DSP_MODE_ROUND 2
/* ISP Generic Cmd Buffer Blob types */
#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0
#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1
#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2
/* Query devices */
/**
* struct cam_isp_dev_cap_info - A cap info for particular hw type
*
* @hw_type: Hardware type for the cap info
* @reserved: reserved field for alignment
* @hw_version: Hardware version
*
*/
struct cam_isp_dev_cap_info {
uint32_t hw_type;
uint32_t reserved;
struct cam_hw_version hw_version;
};
/**
* struct cam_isp_query_cap_cmd - ISP query device capability payload
*
* @device_iommu: returned iommu handles for device
* @cdm_iommu: returned iommu handles for cdm
* @num_dev: returned number of device capabilities
* @reserved: reserved field for alignment
* @dev_caps: returned device capability array
*
*/
struct cam_isp_query_cap_cmd {
struct cam_iommu_handle device_iommu;
struct cam_iommu_handle cdm_iommu;
int32_t num_dev;
uint32_t reserved;
struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX];
};
/* Acquire Device */
/**
* struct cam_isp_out_port_info - An output port resource info
*
* @res_type: output resource type defined in file
* cam_isp_vfe.h or cam_isp_ife.h
* @format: output format of the resource
* @wdith: output width in pixels
* @height: output height in lines
* @comp_grp_id: composite group id for the resource.
* @split_point: split point in pixels for the dual VFE.
* @secure_mode: flag to tell if output should be run in secure
* mode or not. See cam_defs.h for definition
* @reserved: reserved field for alignment
*
*/
struct cam_isp_out_port_info {
uint32_t res_type;
uint32_t format;
uint32_t width;
uint32_t height;
uint32_t comp_grp_id;
uint32_t split_point;
uint32_t secure_mode;
uint32_t reserved;
};
/**
* struct cam_isp_in_port_info - An input port resource info
*
* @res_type: input resource type define in file
* cam_isp_vfe.h or cam_isp_ife.h
* @lane_type: lane type: c-phy or d-phy.
* @lane_num: active lane number
* @lane_cfg: lane configurations: 4 bits per lane
* @vc: input virtual channel number
* @dt: input data type number
* @format: input format
* @test_pattern: test pattern for the testgen
* @usage_type: whether dual vfe is required
* @left_start: left input start offset in pixels
* @left_stop: left input stop offset in pixels
* @left_width: left input width in pixels
* @right_start: right input start offset in pixels.
* Only for Dual VFE
* @right_stop: right input stop offset in pixels.
* Only for Dual VFE
* @right_width: right input width in pixels.
* Only for dual VFE
* @line_start: top of the line number
* @line_stop: bottome of the line number
* @height: input height in lines
* @pixel_clk; sensor output clock
* @batch_size: batch size for HFR mode
* @dsp_mode: DSP stream mode (Defines as CAM_ISP_DSP_MODE_*)
* @hbi_cnt: HBI count for the camif input
* @reserved: Reserved field for alignment
* @num_out_res: number of the output resource associated
* @data: payload that contains the output resources
*
*/
struct cam_isp_in_port_info {
uint32_t res_type;
uint32_t lane_type;
uint32_t lane_num;
uint32_t lane_cfg;
uint32_t vc;
uint32_t dt;
uint32_t format;
uint32_t test_pattern;
uint32_t usage_type;
uint32_t left_start;
uint32_t left_stop;
uint32_t left_width;
uint32_t right_start;
uint32_t right_stop;
uint32_t right_width;
uint32_t line_start;
uint32_t line_stop;
uint32_t height;
uint32_t pixel_clk;
uint32_t batch_size;
uint32_t dsp_mode;
uint32_t hbi_cnt;
uint32_t custom_csid;
uint32_t reserved;
uint32_t num_out_res;
struct cam_isp_out_port_info data[1];
};
/**
* struct cam_isp_resource - A resource bundle
*
* @resoruce_id: resource id for the resource bundle
* @length: length of the while resource blob
* @handle_type: type of the resource handle
* @reserved: reserved field for alignment
* @res_hdl: resource handle that points to the
* resource array;
*
*/
struct cam_isp_resource {
uint32_t resource_id;
uint32_t length;
uint32_t handle_type;
uint32_t reserved;
uint64_t res_hdl;
};
/**
* struct cam_isp_port_hfr_config - HFR configuration for this port
*
* @resource_type: Resource type
* @subsample_pattern: Subsample pattern. Used in HFR mode. It
* should be consistent with batchSize and
* CAMIF programming.
* @subsample_period: Subsample period. Used in HFR mode. It
* should be consistent with batchSize and
* CAMIF programming.
* @framedrop_pattern: Framedrop pattern
* @framedrop_period: Framedrop period
* @reserved: Reserved for alignment
*/
struct cam_isp_port_hfr_config {
uint32_t resource_type;
uint32_t subsample_pattern;
uint32_t subsample_period;
uint32_t framedrop_pattern;
uint32_t framedrop_period;
uint32_t reserved;
} __attribute__((packed));
/**
* struct cam_isp_resource_hfr_config - Resource HFR configuration
*
* @num_ports: Number of ports
* @reserved: Reserved for alignment
* @port_hfr_config: HFR configuration for each IO port
*/
struct cam_isp_resource_hfr_config {
uint32_t num_ports;
uint32_t reserved;
struct cam_isp_port_hfr_config port_hfr_config[1];
} __attribute__((packed));
/**
* struct cam_isp_dual_split_params - dual isp spilt parameters
*
* @split_point: Split point information x, where (0 < x < width)
* left ISP's input ends at x + righ padding and
* Right ISP's input starts at x - left padding
* @right_padding: Padding added past the split point for left
* ISP's input
* @left_padding: Padding added before split point for right
* ISP's input
* @reserved: Reserved filed for alignment
*
*/
struct cam_isp_dual_split_params {
uint32_t split_point;
uint32_t right_padding;
uint32_t left_padding;
uint32_t reserved;
};
/**
* struct cam_isp_dual_stripe_config - stripe config per bus client
*
* @offset: Start horizontal offset relative to
* output buffer
* In UBWC mode, this value indicates the H_INIT
* value in pixel
* @width: Width of the stripe in bytes
* @tileconfig Ubwc meta tile config. Contain the partial
* tile info
* @port_id: port id of ISP output
*
*/
struct cam_isp_dual_stripe_config {
uint32_t offset;
uint32_t width;
uint32_t tileconfig;
uint32_t port_id;
};
/**
* struct cam_isp_dual_config - dual isp configuration
*
* @num_ports Number of isp output ports
* @reserved Reserved field for alignment
* @split_params: Inpput split parameters
* @stripes: Stripe information
*
*/
struct cam_isp_dual_config {
uint32_t num_ports;
uint32_t reserved;
struct cam_isp_dual_split_params split_params;
struct cam_isp_dual_stripe_config stripes[1];
} __attribute__((packed));
/**
* struct cam_isp_clock_config - Clock configuration
*
* @usage_type: Usage type (Single/Dual)
* @num_rdi: Number of RDI votes
* @left_pix_hz: Pixel Clock for Left ISP
* @right_pix_hz: Pixel Clock for Right ISP, valid only if Dual
* @rdi_hz: RDI Clock. ISP clock will be max of RDI and
* PIX clocks. For a particular context which ISP
* HW the RDI is allocated to is not known to UMD.
* Hence pass the clock and let KMD decide.
*/
struct cam_isp_clock_config {
uint32_t usage_type;
uint32_t num_rdi;
uint64_t left_pix_hz;
uint64_t right_pix_hz;
uint64_t rdi_hz[1];
} __attribute__((packed));
/**
* struct cam_isp_bw_vote - Bandwidth vote information
*
* @resource_id: Resource ID
* @reserved: Reserved field for alignment
* @cam_bw_bps: Bandwidth vote for CAMNOC
* @ext_bw_bps: Bandwidth vote for path-to-DDR after CAMNOC
*/
struct cam_isp_bw_vote {
uint32_t resource_id;
uint32_t reserved;
uint64_t cam_bw_bps;
uint64_t ext_bw_bps;
} __attribute__((packed));
/**
* struct cam_isp_bw_config - Bandwidth configuration
*
* @usage_type: Usage type (Single/Dual)
* @num_rdi: Number of RDI votes
* @left_pix_vote: Bandwidth vote for left ISP
* @right_pix_vote: Bandwidth vote for right ISP
* @rdi_vote: RDI bandwidth requirements
*/
struct cam_isp_bw_config {
uint32_t usage_type;
uint32_t num_rdi;
struct cam_isp_bw_vote left_pix_vote;
struct cam_isp_bw_vote right_pix_vote;
struct cam_isp_bw_vote rdi_vote[1];
} __attribute__((packed));
#endif /* __UAPI_CAM_ISP_H__ */

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#ifndef __UAPI_CAM_ISP_IFE_H__
#define __UAPI_CAM_ISP_IFE_H__
/* IFE output port resource type (global unique)*/
#define CAM_ISP_IFE_OUT_RES_BASE 0x3000
#define CAM_ISP_IFE_OUT_RES_FULL (CAM_ISP_IFE_OUT_RES_BASE + 0)
#define CAM_ISP_IFE_OUT_RES_DS4 (CAM_ISP_IFE_OUT_RES_BASE + 1)
#define CAM_ISP_IFE_OUT_RES_DS16 (CAM_ISP_IFE_OUT_RES_BASE + 2)
#define CAM_ISP_IFE_OUT_RES_RAW_DUMP (CAM_ISP_IFE_OUT_RES_BASE + 3)
#define CAM_ISP_IFE_OUT_RES_FD (CAM_ISP_IFE_OUT_RES_BASE + 4)
#define CAM_ISP_IFE_OUT_RES_PDAF (CAM_ISP_IFE_OUT_RES_BASE + 5)
#define CAM_ISP_IFE_OUT_RES_RDI_0 (CAM_ISP_IFE_OUT_RES_BASE + 6)
#define CAM_ISP_IFE_OUT_RES_RDI_1 (CAM_ISP_IFE_OUT_RES_BASE + 7)
#define CAM_ISP_IFE_OUT_RES_RDI_2 (CAM_ISP_IFE_OUT_RES_BASE + 8)
#define CAM_ISP_IFE_OUT_RES_RDI_3 (CAM_ISP_IFE_OUT_RES_BASE + 9)
#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BE (CAM_ISP_IFE_OUT_RES_BASE + 10)
#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 11)
#define CAM_ISP_IFE_OUT_RES_STATS_TL_BG (CAM_ISP_IFE_OUT_RES_BASE + 12)
#define CAM_ISP_IFE_OUT_RES_STATS_BF (CAM_ISP_IFE_OUT_RES_BASE + 13)
#define CAM_ISP_IFE_OUT_RES_STATS_AWB_BG (CAM_ISP_IFE_OUT_RES_BASE + 14)
#define CAM_ISP_IFE_OUT_RES_STATS_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 15)
#define CAM_ISP_IFE_OUT_RES_STATS_RS (CAM_ISP_IFE_OUT_RES_BASE + 16)
#define CAM_ISP_IFE_OUT_RES_STATS_CS (CAM_ISP_IFE_OUT_RES_BASE + 17)
#define CAM_ISP_IFE_OUT_RES_STATS_IHIST (CAM_ISP_IFE_OUT_RES_BASE + 18)
#define CAM_ISP_IFE_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_BASE + 19)
/* IFE input port resource type (global unique) */
#define CAM_ISP_IFE_IN_RES_BASE 0x4000
#define CAM_ISP_IFE_IN_RES_TPG (CAM_ISP_IFE_IN_RES_BASE + 0)
#define CAM_ISP_IFE_IN_RES_PHY_0 (CAM_ISP_IFE_IN_RES_BASE + 1)
#define CAM_ISP_IFE_IN_RES_PHY_1 (CAM_ISP_IFE_IN_RES_BASE + 2)
#define CAM_ISP_IFE_IN_RES_PHY_2 (CAM_ISP_IFE_IN_RES_BASE + 3)
#define CAM_ISP_IFE_IN_RES_PHY_3 (CAM_ISP_IFE_IN_RES_BASE + 4)
#define CAM_ISP_IFE_IN_RES_MAX (CAM_ISP_IFE_IN_RES_BASE + 5)
#endif /* __UAPI_CAM_ISP_IFE_H__ */

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#ifndef __UAPI_CAM_ISP_VFE_H__
#define __UAPI_CAM_ISP_VFE_H__
/* VFE output port resource type (global unique) */
#define CAM_ISP_VFE_OUT_RES_BASE 0x1000
#define CAM_ISP_VFE_OUT_RES_ENC (CAM_ISP_VFE_OUT_RES_BASE + 0)
#define CAM_ISP_VFE_OUT_RES_VIEW (CAM_ISP_VFE_OUT_RES_BASE + 1)
#define CAM_ISP_VFE_OUT_RES_VID (CAM_ISP_VFE_OUT_RES_BASE + 2)
#define CAM_ISP_VFE_OUT_RES_RDI_0 (CAM_ISP_VFE_OUT_RES_BASE + 3)
#define CAM_ISP_VFE_OUT_RES_RDI_1 (CAM_ISP_VFE_OUT_RES_BASE + 4)
#define CAM_ISP_VFE_OUT_RES_RDI_2 (CAM_ISP_VFE_OUT_RES_BASE + 5)
#define CAM_ISP_VFE_OUT_RES_RDI_3 (CAM_ISP_VFE_OUT_RES_BASE + 6)
#define CAM_ISP_VFE_OUT_RES_STATS_AEC (CAM_ISP_VFE_OUT_RES_BASE + 7)
#define CAM_ISP_VFE_OUT_RES_STATS_AF (CAM_ISP_VFE_OUT_RES_BASE + 8)
#define CAM_ISP_VFE_OUT_RES_STATS_AWB (CAM_ISP_VFE_OUT_RES_BASE + 9)
#define CAM_ISP_VFE_OUT_RES_STATS_RS (CAM_ISP_VFE_OUT_RES_BASE + 10)
#define CAM_ISP_VFE_OUT_RES_STATS_CS (CAM_ISP_VFE_OUT_RES_BASE + 11)
#define CAM_ISP_VFE_OUT_RES_STATS_IHIST (CAM_ISP_VFE_OUT_RES_BASE + 12)
#define CAM_ISP_VFE_OUT_RES_STATS_SKIN (CAM_ISP_VFE_OUT_RES_BASE + 13)
#define CAM_ISP_VFE_OUT_RES_STATS_BG (CAM_ISP_VFE_OUT_RES_BASE + 14)
#define CAM_ISP_VFE_OUT_RES_STATS_BF (CAM_ISP_VFE_OUT_RES_BASE + 15)
#define CAM_ISP_VFE_OUT_RES_STATS_BE (CAM_ISP_VFE_OUT_RES_BASE + 16)
#define CAM_ISP_VFE_OUT_RES_STATS_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 17)
#define CAM_ISP_VFE_OUT_RES_STATS_BF_SCALE (CAM_ISP_VFE_OUT_RES_BASE + 18)
#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BE (CAM_ISP_VFE_OUT_RES_BASE + 19)
#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 20)
#define CAM_ISP_VFE_OUT_RES_STATS_AEC_BG (CAM_ISP_VFE_OUT_RES_BASE + 21)
#define CAM_ISP_VFE_OUT_RES_CAMIF_RAW (CAM_ISP_VFE_OUT_RES_BASE + 22)
#define CAM_ISP_VFE_OUT_RES_IDEAL_RAW (CAM_ISP_VFE_OUT_RES_BASE + 23)
#define CAM_ISP_VFE_OUT_RES_MAX (CAM_ISP_VFE_OUT_RES_BASE + 24)
/* VFE input port_ resource type (global unique) */
#define CAM_ISP_VFE_IN_RES_BASE 0x2000
#define CAM_ISP_VFE_IN_RES_TPG (CAM_ISP_VFE_IN_RES_BASE + 0)
#define CAM_ISP_VFE_IN_RES_PHY_0 (CAM_ISP_VFE_IN_RES_BASE + 1)
#define CAM_ISP_VFE_IN_RES_PHY_1 (CAM_ISP_VFE_IN_RES_BASE + 2)
#define CAM_ISP_VFE_IN_RES_PHY_2 (CAM_ISP_VFE_IN_RES_BASE + 3)
#define CAM_ISP_VFE_IN_RES_PHY_3 (CAM_ISP_VFE_IN_RES_BASE + 4)
#define CAM_ISP_VFE_IN_RES_FE (CAM_ISP_VFE_IN_RES_BASE + 5)
#define CAM_ISP_VFE_IN_RES_MAX (CAM_ISP_VFE_IN_RES_BASE + 6)
#endif /* __UAPI_CAM_ISP_VFE_H__ */

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#ifndef __UAPI_CAM_JPEG_H__
#define __UAPI_CAM_JPEG_H__
#include "cam_defs.h"
/* enc, dma, cdm(enc/dma) are used in querycap */
#define CAM_JPEG_DEV_TYPE_ENC 0
#define CAM_JPEG_DEV_TYPE_DMA 1
#define CAM_JPEG_DEV_TYPE_MAX 2
#define CAM_JPEG_NUM_DEV_PER_RES_MAX 1
/* definitions needed for jpeg aquire device */
#define CAM_JPEG_RES_TYPE_ENC 0
#define CAM_JPEG_RES_TYPE_DMA 1
#define CAM_JPEG_RES_TYPE_MAX 2
/* packet opcode types */
#define CAM_JPEG_OPCODE_ENC_UPDATE 0
#define CAM_JPEG_OPCODE_DMA_UPDATE 1
/* ENC input port resource type */
#define CAM_JPEG_ENC_INPUT_IMAGE 0x0
/* ENC output port resource type */
#define CAM_JPEG_ENC_OUTPUT_IMAGE 0x1
#define CAM_JPEG_ENC_IO_IMAGES_MAX 0x2
/* DMA input port resource type */
#define CAM_JPEG_DMA_INPUT_IMAGE 0x0
/* DMA output port resource type */
#define CAM_JPEG_DMA_OUTPUT_IMAGE 0x1
#define CAM_JPEG_DMA_IO_IMAGES_MAX 0x2
#define CAM_JPEG_IMAGE_MAX 0x2
/**
* struct cam_jpeg_dev_ver - Device information for particular hw type
*
* This is used to get device version info of JPEG ENC, JPEG DMA
* from hardware and use this info in CAM_QUERY_CAP IOCTL
*
* @size : Size of struct passed
* @dev_type: Hardware type for the cap info(jpeg enc, jpeg dma)
* @hw_ver: Major, minor and incr values of a device version
*/
struct cam_jpeg_dev_ver {
uint32_t size;
uint32_t dev_type;
struct cam_hw_version hw_ver;
};
/**
* struct cam_jpeg_query_cap_cmd - JPEG query device capability payload
*
* @dev_iommu_handle: Jpeg iommu handles for secure/non secure
* modes
* @cdm_iommu_handle: Iommu handles for secure/non secure modes
* @num_enc: Number of encoder
* @num_dma: Number of dma
* @dev_ver: Returned device capability array
*/
struct cam_jpeg_query_cap_cmd {
struct cam_iommu_handle dev_iommu_handle;
struct cam_iommu_handle cdm_iommu_handle;
uint32_t num_enc;
uint32_t num_dma;
struct cam_jpeg_dev_ver dev_ver[CAM_JPEG_DEV_TYPE_MAX];
};
/**
* struct cam_jpeg_res_info - JPEG output resource info
*
* @format: Format of the resource
* @width: Width in pixels
* @height: Height in lines
* @fps: Fps
*/
struct cam_jpeg_res_info {
uint32_t format;
uint32_t width;
uint32_t height;
uint32_t fps;
};
/**
* struct cam_jpeg_acquire_dev_info - An JPEG device info
*
* @dev_type: Device type (ENC/DMA)
* @reserved: Reserved Bytes
* @in_res: In resource info
* @in_res: Iut resource info
*/
struct cam_jpeg_acquire_dev_info {
uint32_t dev_type;
uint32_t reserved;
struct cam_jpeg_res_info in_res;
struct cam_jpeg_res_info out_res;
};
/**
* struct cam_jpeg_config_inout_param_info - JPEG Config time
* input output params
*
* @clk_index: Input Param- clock selection index.(-1 default)
* @output_size: Output Param - jpeg encode/dma output size in
* bytes
*/
struct cam_jpeg_config_inout_param_info {
int32_t clk_index;
int32_t output_size;
};
#endif /* __UAPI_CAM_JPEG_H__ */

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#ifndef __UAPI_CAM_LRME_H__
#define __UAPI_CAM_LRME_H__
#include "cam_defs.h"
/* LRME Resource Types */
enum CAM_LRME_IO_TYPE {
CAM_LRME_IO_TYPE_TAR,
CAM_LRME_IO_TYPE_REF,
CAM_LRME_IO_TYPE_RES,
CAM_LRME_IO_TYPE_DS2,
};
#define CAM_LRME_INPUT_PORT_TYPE_TAR (1 << 0)
#define CAM_LRME_INPUT_PORT_TYPE_REF (1 << 1)
#define CAM_LRME_OUTPUT_PORT_TYPE_DS2 (1 << 0)
#define CAM_LRME_OUTPUT_PORT_TYPE_RES (1 << 1)
#define CAM_LRME_DEV_MAX 1
struct cam_lrme_hw_version {
uint32_t gen;
uint32_t rev;
uint32_t step;
};
struct cam_lrme_dev_cap {
struct cam_lrme_hw_version clc_hw_version;
struct cam_lrme_hw_version bus_rd_hw_version;
struct cam_lrme_hw_version bus_wr_hw_version;
struct cam_lrme_hw_version top_hw_version;
struct cam_lrme_hw_version top_titan_version;
};
/**
* struct cam_lrme_query_cap_cmd - LRME query device capability payload
*
* @dev_iommu_handle: LRME iommu handles for secure/non secure
* modes
* @cdm_iommu_handle: Iommu handles for secure/non secure modes
* @num_devices: number of hardware devices
* @dev_caps: Returned device capability array
*/
struct cam_lrme_query_cap_cmd {
struct cam_iommu_handle device_iommu;
struct cam_iommu_handle cdm_iommu;
uint32_t num_devices;
struct cam_lrme_dev_cap dev_caps[CAM_LRME_DEV_MAX];
};
struct cam_lrme_soc_info {
uint64_t clock_rate;
uint64_t bandwidth;
uint64_t reserved[4];
};
struct cam_lrme_acquire_args {
struct cam_lrme_soc_info lrme_soc_info;
};
#endif /* __UAPI_CAM_LRME_H__ */

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#ifndef __UAPI_LINUX_CAM_REQ_MGR_H
#define __UAPI_LINUX_CAM_REQ_MGR_H
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/media.h>
#include <media/cam_defs.h>
#define CAM_REQ_MGR_VNODE_NAME "cam-req-mgr-devnode"
#define CAM_DEVICE_TYPE_BASE (MEDIA_ENT_F_OLD_BASE)
#define CAM_VNODE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE)
#define CAM_SENSOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 1)
#define CAM_IFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 2)
#define CAM_ICP_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 3)
#define CAM_LRME_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 4)
#define CAM_JPEG_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 5)
#define CAM_FD_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 6)
#define CAM_CPAS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 7)
#define CAM_CSIPHY_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 8)
#define CAM_ACTUATOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 9)
#define CAM_CCI_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 10)
#define CAM_FLASH_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 11)
#define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12)
#define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13)
/* cam_req_mgr hdl info */
#define CAM_REQ_MGR_HDL_IDX_POS 8
#define CAM_REQ_MGR_HDL_IDX_MASK ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1)
#define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK)
/**
* Max handles supported by cam_req_mgr
* It includes both session and device handles
*/
#define CAM_REQ_MGR_MAX_HANDLES 64
#define MAX_LINKS_PER_SESSION 2
/* V4L event type which user space will subscribe to */
#define V4L_EVENT_CAM_REQ_MGR_EVENT (V4L2_EVENT_PRIVATE_START + 0)
/* Specific event ids to get notified in user space */
#define V4L_EVENT_CAM_REQ_MGR_SOF 0
#define V4L_EVENT_CAM_REQ_MGR_ERROR 1
#define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2
/* SOF Event status */
#define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0
#define CAM_REQ_MGR_SOF_EVENT_ERROR 1
/* Link control operations */
#define CAM_REQ_MGR_LINK_ACTIVATE 0
#define CAM_REQ_MGR_LINK_DEACTIVATE 1
/**
* Request Manager : flush_type
* @CAM_REQ_MGR_FLUSH_TYPE_ALL: Req mgr will remove all the pending
* requests from input/processing queue.
* @CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ: Req mgr will remove only particular
* request id from input/processing queue.
* @CAM_REQ_MGR_FLUSH_TYPE_MAX: Max number of the flush type
* @opcode: CAM_REQ_MGR_FLUSH_REQ
*/
#define CAM_REQ_MGR_FLUSH_TYPE_ALL 0
#define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ 1
#define CAM_REQ_MGR_FLUSH_TYPE_MAX 2
/**
* Request Manager : Sync Mode type
* @CAM_REQ_MGR_SYNC_MODE_NO_SYNC: Req mgr will apply non-sync mode for this
* request.
* @CAM_REQ_MGR_SYNC_MODE_SYNC: Req mgr will apply sync mode for this request.
*/
#define CAM_REQ_MGR_SYNC_MODE_NO_SYNC 0
#define CAM_REQ_MGR_SYNC_MODE_SYNC 1
/**
* struct cam_req_mgr_event_data
* @session_hdl: session handle
* @link_hdl: link handle
* @frame_id: frame id
* @reserved: reserved for 64 bit aligngment
* @req_id: request id
* @tv_sec: timestamp in seconds
* @tv_usec: timestamp in micro seconds
*/
struct cam_req_mgr_event_data {
int32_t session_hdl;
int32_t link_hdl;
int32_t frame_id;
int32_t reserved;
int64_t req_id;
uint64_t tv_sec;
uint64_t tv_usec;
};
/**
* struct cam_req_mgr_session_info
* @session_hdl: In/Output param - session_handle
* @opcode1: CAM_REQ_MGR_CREATE_SESSION
* @opcode2: CAM_REQ_MGR_DESTROY_SESSION
*/
struct cam_req_mgr_session_info {
int32_t session_hdl;
int32_t reserved;
};
/**
* struct cam_req_mgr_link_info
* @session_hdl: Input param - Identifier for CSL session
* @num_devices: Input Param - Num of devices to be linked
* @dev_hdls: Input param - List of device handles to be linked
* @link_hdl: Output Param -Identifier for link
* @opcode: CAM_REQ_MGR_LINK
*/
struct cam_req_mgr_link_info {
int32_t session_hdl;
uint32_t num_devices;
int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES];
int32_t link_hdl;
};
/**
* struct cam_req_mgr_unlink_info
* @session_hdl: input param - session handle
* @link_hdl: input param - link handle
* @opcode: CAM_REQ_MGR_UNLINK
*/
struct cam_req_mgr_unlink_info {
int32_t session_hdl;
int32_t link_hdl;
};
/**
* struct cam_req_mgr_flush_info
* @brief: User can tell drivers to flush a particular request id or
* flush all requests from its pending processing queue. Flush is a
* blocking call and driver shall ensure all requests are flushed
* before returning.
* @session_hdl: Input param - Identifier for CSL session
* @link_hdl: Input Param -Identifier for link
* @flush_type: User can cancel a particular req id or can flush
* all requests in queue
* @reserved: reserved for 64 bit aligngment
* @req_id: field is valid only if flush type is cancel request
* for flush all this field value is not considered.
* @opcode: CAM_REQ_MGR_FLUSH_REQ
*/
struct cam_req_mgr_flush_info {
int32_t session_hdl;
int32_t link_hdl;
uint32_t flush_type;
uint32_t reserved;
int64_t req_id;
};
/** struct cam_req_mgr_sched_info
* @session_hdl: Input param - Identifier for CSL session
* @link_hdl: Input Param -Identifier for link
* inluding itself.
* @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this
* flag is set.
* @sync_mode: Type of Sync mode for this request
* @req_id: Input Param - Request Id from which all requests will be flushed
*/
struct cam_req_mgr_sched_request {
int32_t session_hdl;
int32_t link_hdl;
int32_t bubble_enable;
int32_t sync_mode;
int64_t req_id;
};
/**
* struct cam_req_mgr_sync_mode
* @session_hdl: Input param - Identifier for CSL session
* @sync_mode: Input Param - Type of sync mode
* @num_links: Input Param - Num of links in sync mode (Valid only
* when sync_mode is one of SYNC enabled modes)
* @link_hdls: Input Param - Array of link handles to be in sync mode
* (Valid only when sync_mode is one of SYNC
* enabled modes)
* @master_link_hdl: Input Param - To dictate which link's SOF drives system
* (Valid only when sync_mode is one of SYNC
* enabled modes)
*
* @opcode: CAM_REQ_MGR_SYNC_MODE
*/
struct cam_req_mgr_sync_mode {
int32_t session_hdl;
int32_t sync_mode;
int32_t num_links;
int32_t link_hdls[MAX_LINKS_PER_SESSION];
int32_t master_link_hdl;
int32_t reserved;
};
/**
* struct cam_req_mgr_link_control
* @ops: Link operations: activate/deactive
* @session_hdl: Input param - Identifier for CSL session
* @num_links: Input Param - Num of links
* @reserved: reserved field
* @link_hdls: Input Param - Links to be activated/deactivated
*
* @opcode: CAM_REQ_MGR_LINK_CONTROL
*/
struct cam_req_mgr_link_control {
int32_t ops;
int32_t session_hdl;
int32_t num_links;
int32_t reserved;
int32_t link_hdls[MAX_LINKS_PER_SESSION];
};
/**
* cam_req_mgr specific opcode ids
*/
#define CAM_REQ_MGR_CREATE_DEV_NODES (CAM_COMMON_OPCODE_MAX + 1)
#define CAM_REQ_MGR_CREATE_SESSION (CAM_COMMON_OPCODE_MAX + 2)
#define CAM_REQ_MGR_DESTROY_SESSION (CAM_COMMON_OPCODE_MAX + 3)
#define CAM_REQ_MGR_LINK (CAM_COMMON_OPCODE_MAX + 4)
#define CAM_REQ_MGR_UNLINK (CAM_COMMON_OPCODE_MAX + 5)
#define CAM_REQ_MGR_SCHED_REQ (CAM_COMMON_OPCODE_MAX + 6)
#define CAM_REQ_MGR_FLUSH_REQ (CAM_COMMON_OPCODE_MAX + 7)
#define CAM_REQ_MGR_SYNC_MODE (CAM_COMMON_OPCODE_MAX + 8)
#define CAM_REQ_MGR_ALLOC_BUF (CAM_COMMON_OPCODE_MAX + 9)
#define CAM_REQ_MGR_MAP_BUF (CAM_COMMON_OPCODE_MAX + 10)
#define CAM_REQ_MGR_RELEASE_BUF (CAM_COMMON_OPCODE_MAX + 11)
#define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12)
#define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13)
/* end of cam_req_mgr opcodes */
#define CAM_MEM_FLAG_HW_READ_WRITE (1<<0)
#define CAM_MEM_FLAG_HW_READ_ONLY (1<<1)
#define CAM_MEM_FLAG_HW_WRITE_ONLY (1<<2)
#define CAM_MEM_FLAG_KMD_ACCESS (1<<3)
#define CAM_MEM_FLAG_UMD_ACCESS (1<<4)
#define CAM_MEM_FLAG_PROTECTED_MODE (1<<5)
#define CAM_MEM_FLAG_CMD_BUF_TYPE (1<<6)
#define CAM_MEM_FLAG_PIXEL_BUF_TYPE (1<<7)
#define CAM_MEM_FLAG_STATS_BUF_TYPE (1<<8)
#define CAM_MEM_FLAG_PACKET_BUF_TYPE (1<<9)
#define CAM_MEM_FLAG_CACHE (1<<10)
#define CAM_MEM_FLAG_HW_SHARED_ACCESS (1<<11)
#define CAM_MEM_MMU_MAX_HANDLE 16
/* Maximum allowed buffers in existence */
#define CAM_MEM_BUFQ_MAX 1024
#define CAM_MEM_MGR_SECURE_BIT_POS 15
#define CAM_MEM_MGR_HDL_IDX_SIZE 15
#define CAM_MEM_MGR_HDL_FD_SIZE 16
#define CAM_MEM_MGR_HDL_IDX_END_POS 16
#define CAM_MEM_MGR_HDL_FD_END_POS 32
#define CAM_MEM_MGR_HDL_IDX_MASK ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1)
#define GET_MEM_HANDLE(idx, fd) \
((idx & CAM_MEM_MGR_HDL_IDX_MASK) | \
(fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE))) \
#define GET_FD_FROM_HANDLE(hdl) \
(hdl >> (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE)) \
#define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK)
#define CAM_MEM_MGR_SET_SECURE_HDL(hdl, flag) \
((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : \
((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS)))
#define CAM_MEM_MGR_IS_SECURE_HDL(hdl) \
(((hdl) & \
(1<<CAM_MEM_MGR_SECURE_BIT_POS)) >> CAM_MEM_MGR_SECURE_BIT_POS)
/**
* memory allocation type
*/
#define CAM_MEM_DMA_NONE 0
#define CAM_MEM_DMA_BIDIRECTIONAL 1
#define CAM_MEM_DMA_TO_DEVICE 2
#define CAM_MEM_DMA_FROM_DEVICE 3
/**
* memory cache operation
*/
#define CAM_MEM_CLEAN_CACHE 1
#define CAM_MEM_INV_CACHE 2
#define CAM_MEM_CLEAN_INV_CACHE 3
/**
* struct cam_mem_alloc_out_params
* @buf_handle: buffer handle
* @fd: output buffer file descriptor
* @vaddr: virtual address pointer
*/
struct cam_mem_alloc_out_params {
uint32_t buf_handle;
int32_t fd;
uint64_t vaddr;
};
/**
* struct cam_mem_map_out_params
* @buf_handle: buffer handle
* @reserved: reserved for future
* @vaddr: virtual address pointer
*/
struct cam_mem_map_out_params {
uint32_t buf_handle;
uint32_t reserved;
uint64_t vaddr;
};
/**
* struct cam_mem_mgr_alloc_cmd
* @len: size of buffer to allocate
* @align: alignment of the buffer
* @mmu_hdls: array of mmu handles
* @num_hdl: number of handles
* @flags: flags of the buffer
* @out: out params
*/
/* CAM_REQ_MGR_ALLOC_BUF */
struct cam_mem_mgr_alloc_cmd {
uint64_t len;
uint64_t align;
int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE];
uint32_t num_hdl;
uint32_t flags;
struct cam_mem_alloc_out_params out;
};
/**
* struct cam_mem_mgr_map_cmd
* @mmu_hdls: array of mmu handles
* @num_hdl: number of handles
* @flags: flags of the buffer
* @fd: output buffer file descriptor
* @reserved: reserved field
* @out: out params
*/
/* CAM_REQ_MGR_MAP_BUF */
struct cam_mem_mgr_map_cmd {
int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE];
uint32_t num_hdl;
uint32_t flags;
int32_t fd;
uint32_t reserved;
struct cam_mem_map_out_params out;
};
/**
* struct cam_mem_mgr_map_cmd
* @buf_handle: buffer handle
* @reserved: reserved field
*/
/* CAM_REQ_MGR_RELEASE_BUF */
struct cam_mem_mgr_release_cmd {
int32_t buf_handle;
uint32_t reserved;
};
/**
* struct cam_mem_mgr_map_cmd
* @buf_handle: buffer handle
* @ops: cache operations
*/
/* CAM_REQ_MGR_CACHE_OPS */
struct cam_mem_cache_ops_cmd {
int32_t buf_handle;
uint32_t mem_cache_ops;
};
/**
* Request Manager : error message type
* @CAM_REQ_MGR_ERROR_TYPE_DEVICE: Device error message, fatal to session
* @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal
* @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal
*/
#define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0
#define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1
#define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2
/**
* struct cam_req_mgr_error_msg
* @error_type: type of error
* @request_id: request id of frame
* @device_hdl: device handle
* @linke_hdl: link_hdl
* @resource_size: size of the resource
*/
struct cam_req_mgr_error_msg {
uint32_t error_type;
uint32_t request_id;
int32_t device_hdl;
int32_t link_hdl;
uint64_t resource_size;
};
/**
* struct cam_req_mgr_frame_msg
* @request_id: request id of the frame
* @frame_id: frame id of the frame
* @timestamp: timestamp of the frame
* @link_hdl: link handle associated with this message
* @sof_status: sof status success or fail
*/
struct cam_req_mgr_frame_msg {
uint64_t request_id;
uint64_t frame_id;
uint64_t timestamp;
int32_t link_hdl;
uint32_t sof_status;
};
/**
* struct cam_req_mgr_message
* @session_hdl: session to which the frame belongs to
* @reserved: reserved field
* @u: union which can either be error or frame message
*/
struct cam_req_mgr_message {
int32_t session_hdl;
int32_t reserved;
union {
struct cam_req_mgr_error_msg err_msg;
struct cam_req_mgr_frame_msg frame_msg;
} u;
};
#endif /* __UAPI_LINUX_CAM_REQ_MGR_H */

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#ifndef __UAPI_CAM_SENSOR_H__
#define __UAPI_CAM_SENSOR_H__
#include <linux/types.h>
#include <linux/ioctl.h>
#include <media/cam_defs.h>
#define CAM_SENSOR_PROBE_CMD (CAM_COMMON_OPCODE_MAX + 1)
#define CAM_FLASH_MAX_LED_TRIGGERS 3
#define MAX_OIS_NAME_SIZE 32
#define CAM_CSIPHY_SECURE_MODE_ENABLED 1
/**
* struct cam_sensor_query_cap - capabilities info for sensor
*
* @slot_info : Indicates about the slotId or cell Index
* @secure_camera : Camera is in secure/Non-secure mode
* @pos_pitch : Sensor position pitch
* @pos_roll : Sensor position roll
* @pos_yaw : Sensor position yaw
* @actuator_slot_id : Actuator slot id which connected to sensor
* @eeprom_slot_id : EEPROM slot id which connected to sensor
* @ois_slot_id : OIS slot id which connected to sensor
* @flash_slot_id : Flash slot id which connected to sensor
* @csiphy_slot_id : CSIphy slot id which connected to sensor
*
*/
struct cam_sensor_query_cap {
uint32_t slot_info;
uint32_t secure_camera;
uint32_t pos_pitch;
uint32_t pos_roll;
uint32_t pos_yaw;
uint32_t actuator_slot_id;
uint32_t eeprom_slot_id;
uint32_t ois_slot_id;
uint32_t flash_slot_id;
uint32_t csiphy_slot_id;
} __attribute__((packed));
/**
* struct cam_csiphy_query_cap - capabilities info for csiphy
*
* @slot_info : Indicates about the slotId or cell Index
* @version : CSIphy version
* @clk lane : Of the 5 lanes, informs lane configured
* as clock lane
* @reserved
*/
struct cam_csiphy_query_cap {
uint32_t slot_info;
uint32_t version;
uint32_t clk_lane;
uint32_t reserved;
} __attribute__((packed));
/**
* struct cam_actuator_query_cap - capabilities info for actuator
*
* @slot_info : Indicates about the slotId or cell Index
* @reserved
*/
struct cam_actuator_query_cap {
uint32_t slot_info;
uint32_t reserved;
} __attribute__((packed));
/**
* struct cam_eeprom_query_cap_t - capabilities info for eeprom
*
* @slot_info : Indicates about the slotId or cell Index
* @eeprom_kernel_probe : Indicates about the kernel or userspace probe
*/
struct cam_eeprom_query_cap_t {
uint32_t slot_info;
uint16_t eeprom_kernel_probe;
uint16_t reserved;
} __attribute__((packed));
/**
* struct cam_ois_query_cap_t - capabilities info for ois
*
* @slot_info : Indicates about the slotId or cell Index
*/
struct cam_ois_query_cap_t {
uint32_t slot_info;
uint16_t reserved;
} __attribute__((packed));
/**
* struct cam_cmd_i2c_info - Contains slave I2C related info
*
* @slave_addr : Slave address
* @i2c_freq_mode : 4 bits are used for I2c freq mode
* @cmd_type : Explains type of command
*/
struct cam_cmd_i2c_info {
uint16_t slave_addr;
uint8_t i2c_freq_mode;
uint8_t cmd_type;
} __attribute__((packed));
/**
* struct cam_ois_opcode - Contains OIS opcode
*
* @prog : OIS FW prog register address
* @coeff : OIS FW coeff register address
* @pheripheral : OIS pheripheral
* @memory : OIS memory
*/
struct cam_ois_opcode {
uint32_t prog;
uint32_t coeff;
uint32_t pheripheral;
uint32_t memory;
} __attribute__((packed));
/**
* struct cam_cmd_ois_info - Contains OIS slave info
*
* @slave_addr : OIS i2c slave address
* @i2c_freq_mode : i2c frequency mode
* @cmd_type : Explains type of command
* @ois_fw_flag : indicates if fw is present or not
* @is_ois_calib : indicates the calibration data is available
* @ois_name : OIS name
* @opcode : opcode
*/
struct cam_cmd_ois_info {
uint16_t slave_addr;
uint8_t i2c_freq_mode;
uint8_t cmd_type;
uint8_t ois_fw_flag;
uint8_t is_ois_calib;
char ois_name[MAX_OIS_NAME_SIZE];
struct cam_ois_opcode opcode;
} __attribute__((packed));
/**
* struct cam_cmd_probe - Contains sensor slave info
*
* @data_type : Slave register data type
* @addr_type : Slave register address type
* @op_code : Don't Care
* @cmd_type : Explains type of command
* @reg_addr : Slave register address
* @expected_data : Data expected at slave register address
* @data_mask : Data mask if only few bits are valid
* @camera_id : Indicates the slot to which camera
* needs to be probed
* @reserved
*/
struct cam_cmd_probe {
uint8_t data_type;
uint8_t addr_type;
uint8_t op_code;
uint8_t cmd_type;
uint32_t reg_addr;
uint32_t expected_data;
uint32_t data_mask;
uint16_t camera_id;
uint16_t reserved;
} __attribute__((packed));
/**
* struct cam_power_settings - Contains sensor power setting info
*
* @power_seq_type : Type of power sequence
* @reserved
* @config_val_low : Lower 32 bit value configuration value
* @config_val_high : Higher 32 bit value configuration value
*
*/
struct cam_power_settings {
uint16_t power_seq_type;
uint16_t reserved;
uint32_t config_val_low;
uint32_t config_val_high;
} __attribute__((packed));
/**
* struct cam_cmd_power - Explains about the power settings
*
* @count : Number of power settings follows
* @reserved
* @cmd_type : Explains type of command
* @power_settings : Contains power setting info
*/
struct cam_cmd_power {
uint16_t count;
uint8_t reserved;
uint8_t cmd_type;
struct cam_power_settings power_settings[1];
} __attribute__((packed));
/**
* struct i2c_rdwr_header - header of READ/WRITE I2C command
*
* @ count : Number of registers / data / reg-data pairs
* @ op_code : Operation code
* @ cmd_type : Command buffer type
* @ data_type : I2C data type
* @ addr_type : I2C address type
* @ reserved
*/
struct i2c_rdwr_header {
uint16_t count;
uint8_t op_code;
uint8_t cmd_type;
uint8_t data_type;
uint8_t addr_type;
uint16_t reserved;
} __attribute__((packed));
/**
* struct i2c_random_wr_payload - payload for I2C random write
*
* @ reg_addr : Register address
* @ reg_data : Register data
*
*/
struct i2c_random_wr_payload {
uint32_t reg_addr;
uint32_t reg_data;
} __attribute__((packed));
/**
* struct cam_cmd_i2c_random_wr - I2C random write command
* @ header : header of READ/WRITE I2C command
* @ random_wr_payload : payload for I2C random write
*/
struct cam_cmd_i2c_random_wr {
struct i2c_rdwr_header header;
struct i2c_random_wr_payload random_wr_payload[1];
} __attribute__((packed));
/**
* struct cam_cmd_read - I2C read command
* @ reg_data : Register data
* @ reserved
*/
struct cam_cmd_read {
uint32_t reg_data;
uint32_t reserved;
} __attribute__((packed));
/**
* struct cam_cmd_i2c_continuous_wr - I2C continuous write command
* @ header : header of READ/WRITE I2C command
* @ reg_addr : Register address
* @ data_read : I2C read command
*/
struct cam_cmd_i2c_continuous_wr {
struct i2c_rdwr_header header;
uint32_t reg_addr;
struct cam_cmd_read data_read[1];
} __attribute__((packed));
/**
* struct cam_cmd_i2c_random_rd - I2C random read command
* @ header : header of READ/WRITE I2C command
* @ data_read : I2C read command
*/
struct cam_cmd_i2c_random_rd {
struct i2c_rdwr_header header;
struct cam_cmd_read data_read[1];
} __attribute__((packed));
/**
* struct cam_cmd_i2c_continuous_rd - I2C continuous continuous read command
* @ header : header of READ/WRITE I2C command
* @ reg_addr : Register address
*
*/
struct cam_cmd_i2c_continuous_rd {
struct i2c_rdwr_header header;
uint32_t reg_addr;
} __attribute__((packed));
/**
* struct cam_cmd_conditional_wait - Conditional wait command
* @data_type : Data type
* @addr_type : Address type
* @op_code : Opcode
* @cmd_type : Explains type of command
* @timeout : Timeout for retries
* @reserved
* @reg_addr : Register Address
* @reg_data : Register data
* @data_mask : Data mask if only few bits are valid
* @camera_id : Indicates the slot to which camera
* needs to be probed
*
*/
struct cam_cmd_conditional_wait {
uint8_t data_type;
uint8_t addr_type;
uint8_t op_code;
uint8_t cmd_type;
uint16_t timeout;
uint16_t reserved;
uint32_t reg_addr;
uint32_t reg_data;
uint32_t data_mask;
} __attribute__((packed));
/**
* struct cam_cmd_unconditional_wait - Un-conditional wait command
* @delay : Delay
* @op_code : Opcode
* @cmd_type : Explains type of command
*/
struct cam_cmd_unconditional_wait {
int16_t delay;
uint8_t op_code;
uint8_t cmd_type;
} __attribute__((packed));
/**
* cam_csiphy_info: Provides cmdbuffer structre
* @lane_mask : Lane mask details
* @lane_assign : Lane sensor will be using
* @csiphy_3phase : Total number of lanes
* @combo_mode : Info regarding combo_mode is enable / disable
* @lane_cnt : Total number of lanes
* @secure_mode : Secure mode flag to enable / disable
* @3phase : Details whether 3Phase / 2Phase operation
* @settle_time : Settling time in ms
* @data_rate : Data rate
*
*/
struct cam_csiphy_info {
uint16_t lane_mask;
uint16_t lane_assign;
uint8_t csiphy_3phase;
uint8_t combo_mode;
uint8_t lane_cnt;
uint8_t secure_mode;
uint64_t settle_time;
uint64_t data_rate;
} __attribute__((packed));
/**
* cam_csiphy_acquire_dev_info : Information needed for
* csiphy at the time of acquire
* @combo_mode : Indicates the device mode of operation
* @reserved
*
*/
struct cam_csiphy_acquire_dev_info {
uint32_t combo_mode;
uint32_t reserved;
} __attribute__((packed));
/**
* cam_sensor_acquire_dev : Updates sensor acuire cmd
* @device_handle : Updates device handle
* @session_handle : Session handle for acquiring device
* @handle_type : Resource handle type
* @reserved
* @info_handle : Handle to additional info
* needed for sensor sub modules
*
*/
struct cam_sensor_acquire_dev {
uint32_t session_handle;
uint32_t device_handle;
uint32_t handle_type;
uint32_t reserved;
uint64_t info_handle;
} __attribute__((packed));
/**
* cam_sensor_streamon_dev : StreamOn command for the sensor
* @session_handle : Session handle for acquiring device
* @device_handle : Updates device handle
* @handle_type : Resource handle type
* @reserved
* @info_handle : Information Needed at the time of streamOn
*
*/
struct cam_sensor_streamon_dev {
uint32_t session_handle;
uint32_t device_handle;
uint32_t handle_type;
uint32_t reserved;
uint64_t info_handle;
} __attribute__((packed));
/**
* struct cam_flash_init : Init command for the flash
* @flash_type : flash hw type
* @reserved
* @cmd_type : command buffer type
*/
struct cam_flash_init {
uint8_t flash_type;
uint16_t reserved;
uint8_t cmd_type;
} __attribute__((packed));
/**
* struct cam_flash_set_rer : RedEyeReduction command buffer
*
* @count : Number of flash leds
* @opcode : Command buffer opcode
* CAM_FLASH_FIRE_RER
* @cmd_type : command buffer operation type
* @num_iteration : Number of led turn on/off sequence
* @reserved
* @led_on_delay_ms : flash led turn on time in ms
* @led_off_delay_ms : flash led turn off time in ms
* @led_current_ma : flash led current in ma
*
*/
struct cam_flash_set_rer {
uint16_t count;
uint8_t opcode;
uint8_t cmd_type;
uint16_t num_iteration;
uint16_t reserved;
uint32_t led_on_delay_ms;
uint32_t led_off_delay_ms;
uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS];
} __attribute__((packed));
/**
* struct cam_flash_set_on_off : led turn on/off command buffer
*
* @count : Number of Flash leds
* @opcode : command buffer opcodes
* CAM_FLASH_FIRE_LOW
* CAM_FLASH_FIRE_HIGH
* CAM_FLASH_OFF
* @cmd_type : command buffer operation type
* @led_current_ma : flash led current in ma
*
*/
struct cam_flash_set_on_off {
uint16_t count;
uint8_t opcode;
uint8_t cmd_type;
uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS];
} __attribute__((packed));
/**
* struct cam_flash_query_curr : query current command buffer
*
* @reserved
* @opcode : command buffer opcode
* @cmd_type : command buffer operation type
* @query_current_ma : battery current in ma
*
*/
struct cam_flash_query_curr {
uint16_t reserved;
uint8_t opcode;
uint8_t cmd_type;
uint32_t query_current_ma;
} __attribute__ ((packed));
/**
* struct cam_flash_query_cap : capabilities info for flash
*
* @slot_info : Indicates about the slotId or cell Index
* @max_current_flash : max supported current for flash
* @max_duration_flash : max flash turn on duration
* @max_current_torch : max supported current for torch
*
*/
struct cam_flash_query_cap_info {
uint32_t slot_info;
uint32_t max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS];
uint32_t max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS];
uint32_t max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS];
} __attribute__ ((packed));
#endif

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/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CAM_SENSOR_CMN_HEADER_
#define _CAM_SENSOR_CMN_HEADER_
#include <stdbool.h>
#include <media/cam_sensor.h>
#include <media/cam_req_mgr.h>
#define MAX_REGULATOR 5
#define MAX_POWER_CONFIG 12
#define MAX_PER_FRAME_ARRAY 32
#define BATCH_SIZE_MAX 16
#define CAM_SENSOR_NAME "cam-sensor"
#define CAM_ACTUATOR_NAME "cam-actuator"
#define CAM_CSIPHY_NAME "cam-csiphy"
#define CAM_FLASH_NAME "cam-flash"
#define CAM_EEPROM_NAME "cam-eeprom"
#define CAM_OIS_NAME "cam-ois"
#define MAX_SYSTEM_PIPELINE_DELAY 2
#define CAM_PKT_NOP_OPCODE 127
enum camera_sensor_cmd_type {
CAMERA_SENSOR_CMD_TYPE_INVALID,
CAMERA_SENSOR_CMD_TYPE_PROBE,
CAMERA_SENSOR_CMD_TYPE_PWR_UP,
CAMERA_SENSOR_CMD_TYPE_PWR_DOWN,
CAMERA_SENSOR_CMD_TYPE_I2C_INFO,
CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR,
CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_RD,
CAMERA_SENSOR_CMD_TYPE_I2C_CONT_WR,
CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD,
CAMERA_SENSOR_CMD_TYPE_WAIT,
CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO,
CAMERA_SENSOR_FLASH_CMD_TYPE_FIRE,
CAMERA_SENSOR_FLASH_CMD_TYPE_RER,
CAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR,
CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET,
CAMERA_SENSOR_CMD_TYPE_RD_DATA,
CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE,
CAMERA_SENSOR_CMD_TYPE_MAX,
};
enum camera_sensor_i2c_op_code {
CAMERA_SENSOR_I2C_OP_INVALID,
CAMERA_SENSOR_I2C_OP_RNDM_WR,
CAMERA_SENSOR_I2C_OP_RNDM_WR_VERF,
CAMERA_SENSOR_I2C_OP_CONT_WR_BRST,
CAMERA_SENSOR_I2C_OP_CONT_WR_BRST_VERF,
CAMERA_SENSOR_I2C_OP_CONT_WR_SEQN,
CAMERA_SENSOR_I2C_OP_CONT_WR_SEQN_VERF,
CAMERA_SENSOR_I2C_OP_MAX,
};
enum camera_sensor_wait_op_code {
CAMERA_SENSOR_WAIT_OP_INVALID,
CAMERA_SENSOR_WAIT_OP_COND,
CAMERA_SENSOR_WAIT_OP_HW_UCND,
CAMERA_SENSOR_WAIT_OP_SW_UCND,
CAMERA_SENSOR_WAIT_OP_MAX,
};
enum camera_flash_opcode {
CAMERA_SENSOR_FLASH_OP_INVALID,
CAMERA_SENSOR_FLASH_OP_OFF,
CAMERA_SENSOR_FLASH_OP_FIRELOW,
CAMERA_SENSOR_FLASH_OP_FIREHIGH,
CAMERA_SENSOR_FLASH_OP_MAX,
};
enum camera_sensor_i2c_type {
CAMERA_SENSOR_I2C_TYPE_INVALID,
CAMERA_SENSOR_I2C_TYPE_BYTE,
CAMERA_SENSOR_I2C_TYPE_WORD,
CAMERA_SENSOR_I2C_TYPE_3B,
CAMERA_SENSOR_I2C_TYPE_DWORD,
CAMERA_SENSOR_I2C_TYPE_MAX,
};
enum i2c_freq_mode {
I2C_STANDARD_MODE,
I2C_FAST_MODE,
I2C_CUSTOM_MODE,
I2C_FAST_PLUS_MODE,
I2C_MAX_MODES,
};
enum position_roll {
ROLL_0 = 0,
ROLL_90 = 90,
ROLL_180 = 180,
ROLL_270 = 270,
ROLL_INVALID = 360,
};
enum position_yaw {
FRONT_CAMERA_YAW = 0,
REAR_CAMERA_YAW = 180,
INVALID_YAW = 360,
};
enum position_pitch {
LEVEL_PITCH = 0,
INVALID_PITCH = 360,
};
enum sensor_sub_module {
SUB_MODULE_SENSOR,
SUB_MODULE_ACTUATOR,
SUB_MODULE_EEPROM,
SUB_MODULE_LED_FLASH,
SUB_MODULE_CSID,
SUB_MODULE_CSIPHY,
SUB_MODULE_OIS,
SUB_MODULE_EXT,
SUB_MODULE_MAX,
};
enum msm_camera_power_seq_type {
SENSOR_MCLK,
SENSOR_VANA,
SENSOR_VDIG,
SENSOR_VIO,
SENSOR_VAF,
SENSOR_VAF_PWDM,
SENSOR_CUSTOM_REG1,
SENSOR_CUSTOM_REG2,
SENSOR_RESET,
SENSOR_STANDBY,
SENSOR_CUSTOM_GPIO1,
SENSOR_CUSTOM_GPIO2,
SENSOR_SEQ_TYPE_MAX,
};
enum cam_sensor_packet_opcodes {
CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON,
CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE,
CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG,
CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE,
CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG,
CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF,
CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP = 127
};
enum cam_actuator_packet_opcodes {
CAM_ACTUATOR_PACKET_OPCODE_INIT,
CAM_ACTUATOR_PACKET_AUTO_MOVE_LENS,
CAM_ACTUATOR_PACKET_MANUAL_MOVE_LENS
};
enum cam_eeprom_packet_opcodes {
CAM_EEPROM_PACKET_OPCODE_INIT
};
enum cam_ois_packet_opcodes {
CAM_OIS_PACKET_OPCODE_INIT,
CAM_OIS_PACKET_OPCODE_OIS_CONTROL
};
enum msm_bus_perf_setting {
S_INIT,
S_PREVIEW,
S_VIDEO,
S_CAPTURE,
S_ZSL,
S_STEREO_VIDEO,
S_STEREO_CAPTURE,
S_DEFAULT,
S_LIVESHOT,
S_DUAL,
S_EXIT
};
enum msm_camera_device_type_t {
MSM_CAMERA_I2C_DEVICE,
MSM_CAMERA_PLATFORM_DEVICE,
MSM_CAMERA_SPI_DEVICE,
};
enum cam_flash_device_type {
CAMERA_FLASH_DEVICE_TYPE_PMIC = 0,
CAMERA_FLASH_DEVICE_TYPE_I2C,
CAMERA_FLASH_DEVICE_TYPE_GPIO,
};
enum cci_i2c_master_t {
MASTER_0,
MASTER_1,
MASTER_MAX,
};
enum camera_vreg_type {
VREG_TYPE_DEFAULT,
VREG_TYPE_CUSTOM,
};
enum cam_sensor_i2c_cmd_type {
CAM_SENSOR_I2C_WRITE_RANDOM,
CAM_SENSOR_I2C_WRITE_BURST,
CAM_SENSOR_I2C_WRITE_SEQ,
CAM_SENSOR_I2C_READ,
CAM_SENSOR_I2C_POLL
};
struct common_header {
uint16_t first_word;
uint8_t third_byte;
uint8_t cmd_type;
};
struct camera_vreg_t {
const char *reg_name;
int min_voltage;
int max_voltage;
int op_mode;
uint32_t delay;
const char *custom_vreg_name;
enum camera_vreg_type type;
};
struct msm_camera_gpio_num_info {
uint16_t gpio_num[SENSOR_SEQ_TYPE_MAX];
uint8_t valid[SENSOR_SEQ_TYPE_MAX];
};
struct msm_cam_clk_info {
const char *clk_name;
long clk_rate;
uint32_t delay;
};
struct msm_pinctrl_info {
struct pinctrl *pinctrl;
struct pinctrl_state *gpio_state_active;
struct pinctrl_state *gpio_state_suspend;
bool use_pinctrl;
};
struct cam_sensor_i2c_reg_array {
uint32_t reg_addr;
uint32_t reg_data;
uint32_t delay;
uint32_t data_mask;
};
struct cam_sensor_i2c_reg_setting {
struct cam_sensor_i2c_reg_array *reg_setting;
unsigned short size;
enum camera_sensor_i2c_type addr_type;
enum camera_sensor_i2c_type data_type;
unsigned short delay;
};
/*struct i2c_settings_list {
struct cam_sensor_i2c_reg_setting i2c_settings;
enum cam_sensor_i2c_cmd_type op_code;
struct list_head list;
};
struct i2c_settings_array {
struct list_head list_head;
int32_t is_settings_valid;
int64_t request_id;
};
struct i2c_data_settings {
struct i2c_settings_array init_settings;
struct i2c_settings_array config_settings;
struct i2c_settings_array streamon_settings;
struct i2c_settings_array streamoff_settings;
struct i2c_settings_array *per_frame;
};*/
struct cam_sensor_power_ctrl_t {
struct device *dev;
struct cam_sensor_power_setting *power_setting;
uint16_t power_setting_size;
struct cam_sensor_power_setting *power_down_setting;
uint16_t power_down_setting_size;
struct msm_camera_gpio_num_info *gpio_num_info;
struct msm_pinctrl_info pinctrl_info;
uint8_t cam_pinctrl_status;
};
struct cam_camera_slave_info {
uint16_t sensor_slave_addr;
uint16_t sensor_id_reg_addr;
uint16_t sensor_id;
uint16_t sensor_id_mask;
};
struct msm_sensor_init_params {
int modes_supported;
unsigned int sensor_mount_angle;
};
enum msm_sensor_camera_id_t {
CAMERA_0,
CAMERA_1,
CAMERA_2,
CAMERA_3,
CAMERA_4,
CAMERA_5,
CAMERA_6,
MAX_CAMERAS,
};
struct msm_sensor_id_info_t {
unsigned short sensor_id_reg_addr;
unsigned short sensor_id;
unsigned short sensor_id_mask;
};
enum msm_sensor_output_format_t {
MSM_SENSOR_BAYER,
MSM_SENSOR_YCBCR,
MSM_SENSOR_META,
};
struct cam_sensor_power_setting {
enum msm_camera_power_seq_type seq_type;
unsigned short seq_val;
long config_val;
unsigned short delay;
void *data[10];
};
struct cam_sensor_board_info {
struct cam_camera_slave_info slave_info;
int32_t sensor_mount_angle;
int32_t secure_mode;
int modes_supported;
int32_t pos_roll;
int32_t pos_yaw;
int32_t pos_pitch;
int32_t subdev_id[SUB_MODULE_MAX];
int32_t subdev_intf[SUB_MODULE_MAX];
const char *misc_regulator;
struct cam_sensor_power_ctrl_t power_info;
};
enum msm_camera_vreg_name_t {
CAM_VDIG,
CAM_VIO,
CAM_VANA,
CAM_VAF,
CAM_V_CUSTOM1,
CAM_V_CUSTOM2,
CAM_VREG_MAX,
};
struct msm_camera_gpio_conf {
void *cam_gpiomux_conf_tbl;
uint8_t cam_gpiomux_conf_tbl_size;
struct gpio *cam_gpio_common_tbl;
uint8_t cam_gpio_common_tbl_size;
struct gpio *cam_gpio_req_tbl;
uint8_t cam_gpio_req_tbl_size;
uint32_t gpio_no_mux;
uint32_t *camera_off_table;
uint8_t camera_off_table_size;
uint32_t *camera_on_table;
uint8_t camera_on_table_size;
struct msm_camera_gpio_num_info *gpio_num_info;
};
/*for tof camera Begin*/
enum EEPROM_DATA_OP_T{
EEPROM_DEFAULT_DATA = 0,
EEPROM_INIT_DATA,
EEPROM_CONFIG_DATA,
EEPROM_STREAMON_DATA,
EEPROM_STREAMOFF_DATA,
EEPROM_OTHER_DATA,
};
/*for tof camera End*/
#endif /* _CAM_SENSOR_CMN_HEADER_ */

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#ifndef __UAPI_CAM_SYNC_H__
#define __UAPI_CAM_SYNC_H__
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/media.h>
#define CAM_SYNC_DEVICE_NAME "cam_sync_device"
/* V4L event which user space will subscribe to */
#define CAM_SYNC_V4L_EVENT (V4L2_EVENT_PRIVATE_START + 0)
/* Specific event ids to get notified in user space */
#define CAM_SYNC_V4L_EVENT_ID_CB_TRIG 0
/* Size of opaque payload sent to kernel for safekeeping until signal time */
#define CAM_SYNC_USER_PAYLOAD_SIZE 2
/* Device type for sync device needed for device discovery */
#define CAM_SYNC_DEVICE_TYPE (MEDIA_ENT_F_OLD_BASE)
#define CAM_SYNC_GET_PAYLOAD_PTR(ev, type) \
(type *)((char *)ev.u.data + sizeof(struct cam_sync_ev_header))
#define CAM_SYNC_GET_HEADER_PTR(ev) \
((struct cam_sync_ev_header *)ev.u.data)
#define CAM_SYNC_STATE_INVALID 0
#define CAM_SYNC_STATE_ACTIVE 1
#define CAM_SYNC_STATE_SIGNALED_SUCCESS 2
#define CAM_SYNC_STATE_SIGNALED_ERROR 3
/**
* struct cam_sync_ev_header - Event header for sync event notification
*
* @sync_obj: Sync object
* @status: Status of the object
*/
struct cam_sync_ev_header {
int32_t sync_obj;
int32_t status;
};
/**
* struct cam_sync_info - Sync object creation information
*
* @name: Optional string representation of the sync object
* @sync_obj: Sync object returned after creation in kernel
*/
struct cam_sync_info {
char name[64];
int32_t sync_obj;
};
/**
* struct cam_sync_signal - Sync object signaling struct
*
* @sync_obj: Sync object to be signaled
* @sync_state: State of the sync object to which it should be signaled
*/
struct cam_sync_signal {
int32_t sync_obj;
uint32_t sync_state;
};
/**
* struct cam_sync_merge - Merge information for sync objects
*
* @sync_objs: Pointer to sync objects
* @num_objs: Number of objects in the array
* @merged: Merged sync object
*/
struct cam_sync_merge {
__u64 sync_objs;
uint32_t num_objs;
int32_t merged;
};
/**
* struct cam_sync_userpayload_info - Payload info from user space
*
* @sync_obj: Sync object for which payload has to be registered for
* @reserved: Reserved
* @payload: Pointer to user payload
*/
struct cam_sync_userpayload_info {
int32_t sync_obj;
uint32_t reserved;
__u64 payload[CAM_SYNC_USER_PAYLOAD_SIZE];
};
/**
* struct cam_sync_wait - Sync object wait information
*
* @sync_obj: Sync object to wait on
* @reserved: Reserved
* @timeout_ms: Timeout in milliseconds
*/
struct cam_sync_wait {
int32_t sync_obj;
uint32_t reserved;
uint64_t timeout_ms;
};
/**
* struct cam_private_ioctl_arg - Sync driver ioctl argument
*
* @id: IOCTL command id
* @size: Size of command payload
* @result: Result of command execution
* @reserved: Reserved
* @ioctl_ptr: Pointer to user data
*/
struct cam_private_ioctl_arg {
__u32 id;
__u32 size;
__u32 result;
__u32 reserved;
__u64 ioctl_ptr;
};
#define CAM_PRIVATE_IOCTL_CMD \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_private_ioctl_arg)
#define CAM_SYNC_CREATE 0
#define CAM_SYNC_DESTROY 1
#define CAM_SYNC_SIGNAL 2
#define CAM_SYNC_MERGE 3
#define CAM_SYNC_REGISTER_PAYLOAD 4
#define CAM_SYNC_DEREGISTER_PAYLOAD 5
#define CAM_SYNC_WAIT 6
#endif /* __UAPI_CAM_SYNC_H__ */

829
third_party/linux/include/msm_cam_sensor.h vendored Normal file
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@@ -0,0 +1,829 @@
#ifndef __LINUX_MSM_CAM_SENSOR_H
#define __LINUX_MSM_CAM_SENSOR_H
#ifdef MSM_CAMERA_BIONIC
#include <sys/types.h>
#endif
//#include <linux/v4l2-mediabus.h>
#include "msm_camsensor_sdk.h"
#include <linux/types.h>
#include <linux/i2c.h>
#ifdef CONFIG_COMPAT
#include <linux/compat.h>
#endif
#define I2C_SEQ_REG_SETTING_MAX 5
#define MSM_SENSOR_MCLK_8HZ 8000000
#define MSM_SENSOR_MCLK_16HZ 16000000
#define MSM_SENSOR_MCLK_24HZ 24000000
#define MAX_SENSOR_NAME 32
#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024
#define MAX_OIS_MOD_NAME_SIZE 32
#define MAX_OIS_NAME_SIZE 32
#define MAX_OIS_REG_SETTINGS 800
#define MOVE_NEAR 0
#define MOVE_FAR 1
#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1
#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1
#define MAX_ACTUATOR_REGION 5
#define MAX_EEPROM_NAME 32
#define MAX_AF_ITERATIONS 3
#define MAX_NUMBER_OF_STEPS 47
#define MAX_REGULATOR 5
#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */
#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
/* 14 BGBG.. GRGR.. */
#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
/* 14 GBGB.. RGRG.. */
#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
/* 14 GRGR.. BGBG.. */
#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
/* 14 RGRG.. GBGB.. */
enum flash_type {
LED_FLASH = 1,
STROBE_FLASH,
GPIO_FLASH
};
enum msm_sensor_resolution_t {
MSM_SENSOR_RES_FULL,
MSM_SENSOR_RES_QTR,
MSM_SENSOR_RES_2,
MSM_SENSOR_RES_3,
MSM_SENSOR_RES_4,
MSM_SENSOR_RES_5,
MSM_SENSOR_RES_6,
MSM_SENSOR_RES_7,
MSM_SENSOR_INVALID_RES,
};
enum msm_camera_stream_type_t {
MSM_CAMERA_STREAM_PREVIEW,
MSM_CAMERA_STREAM_SNAPSHOT,
MSM_CAMERA_STREAM_VIDEO,
MSM_CAMERA_STREAM_INVALID,
};
enum sensor_sub_module_t {
SUB_MODULE_SENSOR,
SUB_MODULE_CHROMATIX,
SUB_MODULE_ACTUATOR,
SUB_MODULE_EEPROM,
SUB_MODULE_LED_FLASH,
SUB_MODULE_STROBE_FLASH,
SUB_MODULE_CSID,
SUB_MODULE_CSID_3D,
SUB_MODULE_CSIPHY,
SUB_MODULE_CSIPHY_3D,
SUB_MODULE_OIS,
SUB_MODULE_EXT,
SUB_MODULE_MAX,
};
enum {
MSM_CAMERA_EFFECT_MODE_OFF,
MSM_CAMERA_EFFECT_MODE_MONO,
MSM_CAMERA_EFFECT_MODE_NEGATIVE,
MSM_CAMERA_EFFECT_MODE_SOLARIZE,
MSM_CAMERA_EFFECT_MODE_SEPIA,
MSM_CAMERA_EFFECT_MODE_POSTERIZE,
MSM_CAMERA_EFFECT_MODE_WHITEBOARD,
MSM_CAMERA_EFFECT_MODE_BLACKBOARD,
MSM_CAMERA_EFFECT_MODE_AQUA,
MSM_CAMERA_EFFECT_MODE_EMBOSS,
MSM_CAMERA_EFFECT_MODE_SKETCH,
MSM_CAMERA_EFFECT_MODE_NEON,
MSM_CAMERA_EFFECT_MODE_MAX
};
enum {
MSM_CAMERA_WB_MODE_AUTO,
MSM_CAMERA_WB_MODE_CUSTOM,
MSM_CAMERA_WB_MODE_INCANDESCENT,
MSM_CAMERA_WB_MODE_FLUORESCENT,
MSM_CAMERA_WB_MODE_WARM_FLUORESCENT,
MSM_CAMERA_WB_MODE_DAYLIGHT,
MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT,
MSM_CAMERA_WB_MODE_TWILIGHT,
MSM_CAMERA_WB_MODE_SHADE,
MSM_CAMERA_WB_MODE_OFF,
MSM_CAMERA_WB_MODE_MAX
};
enum {
MSM_CAMERA_SCENE_MODE_OFF,
MSM_CAMERA_SCENE_MODE_AUTO,
MSM_CAMERA_SCENE_MODE_LANDSCAPE,
MSM_CAMERA_SCENE_MODE_SNOW,
MSM_CAMERA_SCENE_MODE_BEACH,
MSM_CAMERA_SCENE_MODE_SUNSET,
MSM_CAMERA_SCENE_MODE_NIGHT,
MSM_CAMERA_SCENE_MODE_PORTRAIT,
MSM_CAMERA_SCENE_MODE_BACKLIGHT,
MSM_CAMERA_SCENE_MODE_SPORTS,
MSM_CAMERA_SCENE_MODE_ANTISHAKE,
MSM_CAMERA_SCENE_MODE_FLOWERS,
MSM_CAMERA_SCENE_MODE_CANDLELIGHT,
MSM_CAMERA_SCENE_MODE_FIREWORKS,
MSM_CAMERA_SCENE_MODE_PARTY,
MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT,
MSM_CAMERA_SCENE_MODE_THEATRE,
MSM_CAMERA_SCENE_MODE_ACTION,
MSM_CAMERA_SCENE_MODE_AR,
MSM_CAMERA_SCENE_MODE_FACE_PRIORITY,
MSM_CAMERA_SCENE_MODE_BARCODE,
MSM_CAMERA_SCENE_MODE_HDR,
MSM_CAMERA_SCENE_MODE_MAX
};
enum csid_cfg_type_t {
CSID_INIT,
CSID_CFG,
CSID_TESTMODE_CFG,
CSID_RELEASE,
};
enum csiphy_cfg_type_t {
CSIPHY_INIT,
CSIPHY_CFG,
CSIPHY_RELEASE,
};
enum camera_vreg_type {
VREG_TYPE_DEFAULT,
VREG_TYPE_CUSTOM,
};
enum sensor_af_t {
SENSOR_AF_FOCUSSED,
SENSOR_AF_NOT_FOCUSSED,
};
enum cci_i2c_master_t {
MASTER_0,
MASTER_1,
MASTER_MAX,
};
struct msm_camera_i2c_array_write_config {
struct msm_camera_i2c_reg_setting conf_array;
uint16_t slave_addr;
};
struct msm_camera_i2c_read_config {
uint16_t slave_addr;
uint16_t reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
uint16_t data;
};
struct msm_camera_csi2_params {
struct msm_camera_csid_params csid_params;
struct msm_camera_csiphy_params csiphy_params;
uint8_t csi_clk_scale_enable;
};
struct msm_camera_csi_lane_params {
uint16_t csi_lane_assign;
uint16_t csi_lane_mask;
};
struct csi_lane_params_t {
uint16_t csi_lane_assign;
uint8_t csi_lane_mask;
uint8_t csi_if;
int8_t csid_core[2];
uint8_t csi_phy_sel;
};
struct msm_sensor_info_t {
char sensor_name[MAX_SENSOR_NAME];
uint32_t session_id;
int32_t subdev_id[SUB_MODULE_MAX];
int32_t subdev_intf[SUB_MODULE_MAX];
uint8_t is_mount_angle_valid;
uint32_t sensor_mount_angle;
int modes_supported;
enum camb_position_t position;
};
struct camera_vreg_t {
const char *reg_name;
int min_voltage;
int max_voltage;
int op_mode;
uint32_t delay;
const char *custom_vreg_name;
enum camera_vreg_type type;
};
struct sensorb_cfg_data {
int cfgtype;
union {
struct msm_sensor_info_t sensor_info;
struct msm_sensor_init_params sensor_init_params;
void *setting;
struct msm_sensor_i2c_sync_params sensor_i2c_sync_params;
} cfg;
};
struct csid_cfg_data {
enum csid_cfg_type_t cfgtype;
union {
uint32_t csid_version;
struct msm_camera_csid_params *csid_params;
struct msm_camera_csid_testmode_parms *csid_testmode_params;
} cfg;
};
struct csiphy_cfg_data {
enum csiphy_cfg_type_t cfgtype;
union {
struct msm_camera_csiphy_params *csiphy_params;
struct msm_camera_csi_lane_params *csi_lane_params;
} cfg;
};
enum eeprom_cfg_type_t {
CFG_EEPROM_GET_INFO,
CFG_EEPROM_GET_CAL_DATA,
CFG_EEPROM_READ_CAL_DATA,
CFG_EEPROM_WRITE_DATA,
CFG_EEPROM_GET_MM_INFO,
CFG_EEPROM_INIT,
};
struct eeprom_get_t {
uint32_t num_bytes;
};
struct eeprom_read_t {
uint8_t *dbuffer;
uint32_t num_bytes;
};
struct eeprom_write_t {
uint8_t *dbuffer;
uint32_t num_bytes;
};
struct eeprom_get_cmm_t {
uint32_t cmm_support;
uint32_t cmm_compression;
uint32_t cmm_size;
};
struct msm_eeprom_info_t {
struct msm_sensor_power_setting_array *power_setting_array;
enum i2c_freq_mode_t i2c_freq_mode;
struct msm_eeprom_memory_map_array *mem_map_array;
};
struct msm_eeprom_cfg_data {
enum eeprom_cfg_type_t cfgtype;
uint8_t is_supported;
union {
char eeprom_name[MAX_SENSOR_NAME];
struct eeprom_get_t get_data;
struct eeprom_read_t read_data;
struct eeprom_write_t write_data;
struct eeprom_get_cmm_t get_cmm_data;
struct msm_eeprom_info_t eeprom_info;
} cfg;
};
#ifdef CONFIG_COMPAT
struct msm_sensor_power_setting32 {
enum msm_sensor_power_seq_type_t seq_type;
uint16_t seq_val;
compat_uint_t config_val;
uint16_t delay;
compat_uptr_t data[10];
};
struct msm_sensor_power_setting_array32 {
struct msm_sensor_power_setting32 power_setting_a[MAX_POWER_CONFIG];
compat_uptr_t power_setting;
uint16_t size;
struct msm_sensor_power_setting32
power_down_setting_a[MAX_POWER_CONFIG];
compat_uptr_t power_down_setting;
uint16_t size_down;
};
struct msm_camera_sensor_slave_info32 {
char sensor_name[32];
char eeprom_name[32];
char actuator_name[32];
char ois_name[32];
char flash_name[32];
enum msm_sensor_camera_id_t camera_id;
uint16_t slave_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type addr_type;
struct msm_sensor_id_info_t sensor_id_info;
struct msm_sensor_power_setting_array32 power_setting_array;
uint8_t is_init_params_valid;
struct msm_sensor_init_params sensor_init_params;
enum msm_sensor_output_format_t output_format;
};
struct msm_camera_csid_lut_params32 {
uint8_t num_cid;
struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];
compat_uptr_t vc_cfg[MAX_CID];
};
struct msm_camera_csid_params32 {
uint8_t lane_cnt;
uint16_t lane_assign;
uint8_t phy_sel;
uint32_t csi_clk;
struct msm_camera_csid_lut_params32 lut_params;
uint8_t csi_3p_sel;
};
struct msm_camera_csi2_params32 {
struct msm_camera_csid_params32 csid_params;
struct msm_camera_csiphy_params csiphy_params;
uint8_t csi_clk_scale_enable;
};
struct csid_cfg_data32 {
enum csid_cfg_type_t cfgtype;
union {
uint32_t csid_version;
compat_uptr_t csid_params;
compat_uptr_t csid_testmode_params;
} cfg;
};
struct eeprom_read_t32 {
compat_uptr_t dbuffer;
uint32_t num_bytes;
};
struct eeprom_write_t32 {
compat_uptr_t dbuffer;
uint32_t num_bytes;
};
struct msm_eeprom_info_t32 {
compat_uptr_t power_setting_array;
enum i2c_freq_mode_t i2c_freq_mode;
compat_uptr_t mem_map_array;
};
struct msm_eeprom_cfg_data32 {
enum eeprom_cfg_type_t cfgtype;
uint8_t is_supported;
union {
char eeprom_name[MAX_SENSOR_NAME];
struct eeprom_get_t get_data;
struct eeprom_read_t32 read_data;
struct eeprom_write_t32 write_data;
struct msm_eeprom_info_t32 eeprom_info;
} cfg;
};
struct msm_camera_i2c_seq_reg_setting32 {
compat_uptr_t reg_setting;
uint16_t size;
enum msm_camera_i2c_reg_addr_type addr_type;
uint16_t delay;
};
#endif
enum msm_sensor_cfg_type_t {
CFG_SET_SLAVE_INFO,
CFG_SLAVE_READ_I2C,
CFG_WRITE_I2C_ARRAY,
CFG_SLAVE_WRITE_I2C_ARRAY,
CFG_WRITE_I2C_SEQ_ARRAY,
CFG_POWER_UP,
CFG_POWER_DOWN,
CFG_SET_STOP_STREAM_SETTING,
CFG_GET_SENSOR_INFO,
CFG_GET_SENSOR_INIT_PARAMS,
CFG_SET_INIT_SETTING,
CFG_SET_RESOLUTION,
CFG_SET_STOP_STREAM,
CFG_SET_START_STREAM,
CFG_SET_SATURATION,
CFG_SET_CONTRAST,
CFG_SET_SHARPNESS,
CFG_SET_ISO,
CFG_SET_EXPOSURE_COMPENSATION,
CFG_SET_ANTIBANDING,
CFG_SET_BESTSHOT_MODE,
CFG_SET_EFFECT,
CFG_SET_WHITE_BALANCE,
CFG_SET_AUTOFOCUS,
CFG_CANCEL_AUTOFOCUS,
CFG_SET_STREAM_TYPE,
CFG_SET_I2C_SYNC_PARAM,
CFG_WRITE_I2C_ARRAY_ASYNC,
CFG_WRITE_I2C_ARRAY_SYNC,
CFG_WRITE_I2C_ARRAY_SYNC_BLOCK,
};
enum msm_actuator_cfg_type_t {
CFG_GET_ACTUATOR_INFO,
CFG_SET_ACTUATOR_INFO,
CFG_SET_DEFAULT_FOCUS,
CFG_MOVE_FOCUS,
CFG_SET_POSITION,
CFG_ACTUATOR_POWERDOWN,
CFG_ACTUATOR_POWERUP,
CFG_ACTUATOR_INIT,
};
enum msm_ois_cfg_type_t {
CFG_OIS_INIT,
CFG_OIS_POWERDOWN,
CFG_OIS_POWERUP,
CFG_OIS_CONTROL,
CFG_OIS_I2C_WRITE_SEQ_TABLE,
};
enum msm_ois_i2c_operation {
MSM_OIS_WRITE = 0,
MSM_OIS_POLL,
};
struct reg_settings_ois_t {
uint16_t reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
uint32_t reg_data;
enum msm_camera_i2c_data_type data_type;
enum msm_ois_i2c_operation i2c_operation;
uint32_t delay;
#define OIS_REG_DATA_SEQ_MAX 128
unsigned char reg_data_seq[OIS_REG_DATA_SEQ_MAX];
uint32_t reg_data_seq_size;
};
struct msm_ois_params_t {
uint16_t data_size;
uint16_t setting_size;
uint32_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type i2c_addr_type;
enum msm_camera_i2c_data_type i2c_data_type;
struct reg_settings_ois_t *settings;
};
struct msm_ois_set_info_t {
struct msm_ois_params_t ois_params;
};
struct msm_actuator_move_params_t {
int8_t dir;
int8_t sign_dir;
int16_t dest_step_pos;
int32_t num_steps;
uint16_t curr_lens_pos;
struct damping_params_t *ringing_params;
};
struct msm_actuator_tuning_params_t {
int16_t initial_code;
uint16_t pwd_step;
uint16_t region_size;
uint32_t total_steps;
struct region_params_t *region_params;
};
struct park_lens_data_t {
uint32_t damping_step;
uint32_t damping_delay;
uint32_t hw_params;
uint32_t max_step;
};
struct msm_actuator_params_t {
enum actuator_type act_type;
uint8_t reg_tbl_size;
uint16_t data_size;
uint16_t init_setting_size;
uint32_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_actuator_addr_type i2c_addr_type;
enum msm_actuator_data_type i2c_data_type;
struct msm_actuator_reg_params_t *reg_tbl_params;
struct reg_settings_t *init_settings;
struct park_lens_data_t park_lens;
};
struct msm_actuator_set_info_t {
struct msm_actuator_params_t actuator_params;
struct msm_actuator_tuning_params_t af_tuning_params;
};
struct msm_actuator_get_info_t {
uint32_t focal_length_num;
uint32_t focal_length_den;
uint32_t f_number_num;
uint32_t f_number_den;
uint32_t f_pix_num;
uint32_t f_pix_den;
uint32_t total_f_dist_num;
uint32_t total_f_dist_den;
uint32_t hor_view_angle_num;
uint32_t hor_view_angle_den;
uint32_t ver_view_angle_num;
uint32_t ver_view_angle_den;
};
enum af_camera_name {
ACTUATOR_MAIN_CAM_0,
ACTUATOR_MAIN_CAM_1,
ACTUATOR_MAIN_CAM_2,
ACTUATOR_MAIN_CAM_3,
ACTUATOR_MAIN_CAM_4,
ACTUATOR_MAIN_CAM_5,
ACTUATOR_WEB_CAM_0,
ACTUATOR_WEB_CAM_1,
ACTUATOR_WEB_CAM_2,
};
struct msm_ois_cfg_data {
int cfgtype;
union {
struct msm_ois_set_info_t set_info;
struct msm_camera_i2c_seq_reg_setting *settings;
} cfg;
};
struct msm_actuator_set_position_t {
uint16_t number_of_steps;
uint32_t hw_params;
uint16_t pos[MAX_NUMBER_OF_STEPS];
uint16_t delay[MAX_NUMBER_OF_STEPS];
};
struct msm_actuator_cfg_data {
int cfgtype;
uint8_t is_af_supported;
union {
struct msm_actuator_move_params_t move;
struct msm_actuator_set_info_t set_info;
struct msm_actuator_get_info_t get_info;
struct msm_actuator_set_position_t setpos;
enum af_camera_name cam_name;
} cfg;
};
enum msm_camera_led_config_t {
MSM_CAMERA_LED_OFF,
MSM_CAMERA_LED_LOW,
MSM_CAMERA_LED_HIGH,
MSM_CAMERA_LED_INIT,
MSM_CAMERA_LED_RELEASE,
};
struct msm_camera_led_cfg_t {
enum msm_camera_led_config_t cfgtype;
int32_t torch_current[MAX_LED_TRIGGERS];
int32_t flash_current[MAX_LED_TRIGGERS];
int32_t flash_duration[MAX_LED_TRIGGERS];
};
struct msm_flash_init_info_t {
enum msm_flash_driver_type flash_driver_type;
uint32_t slave_addr;
enum i2c_freq_mode_t i2c_freq_mode;
struct msm_sensor_power_setting_array *power_setting_array;
struct msm_camera_i2c_reg_setting_array *settings;
};
struct msm_flash_cfg_data_t {
enum msm_flash_cfg_type_t cfg_type;
int32_t flash_current[MAX_LED_TRIGGERS];
int32_t flash_duration[MAX_LED_TRIGGERS];
union {
struct msm_flash_init_info_t *flash_init_info;
struct msm_camera_i2c_reg_setting_array *settings;
} cfg;
};
/* sensor init structures and enums */
enum msm_sensor_init_cfg_type_t {
CFG_SINIT_PROBE,
CFG_SINIT_PROBE_DONE,
CFG_SINIT_PROBE_WAIT_DONE,
};
struct sensor_init_cfg_data {
enum msm_sensor_init_cfg_type_t cfgtype;
struct msm_sensor_info_t probed_info;
char entity_name[MAX_SENSOR_NAME];
union {
void *setting;
} cfg;
};
#define VIDIOC_MSM_SENSOR_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data)
#define VIDIOC_MSM_SENSOR_RELEASE \
_IO('V', BASE_VIDIOC_PRIVATE + 2)
#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \
_IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t)
#define VIDIOC_MSM_CSIPHY_IO_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data)
#define VIDIOC_MSM_CSID_IO_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data)
#define VIDIOC_MSM_ACTUATOR_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data)
#define VIDIOC_MSM_FLASH_LED_DATA_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t)
#define VIDIOC_MSM_EEPROM_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data)
#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \
_IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t)
#define VIDIOC_MSM_SENSOR_INIT_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data)
#define VIDIOC_MSM_OIS_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data)
#define VIDIOC_MSM_FLASH_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t)
#ifdef CONFIG_COMPAT
struct msm_camera_i2c_reg_setting32 {
compat_uptr_t reg_setting;
uint16_t size;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
uint16_t delay;
};
struct msm_camera_i2c_array_write_config32 {
struct msm_camera_i2c_reg_setting32 conf_array;
uint16_t slave_addr;
};
struct msm_actuator_tuning_params_t32 {
int16_t initial_code;
uint16_t pwd_step;
uint16_t region_size;
uint32_t total_steps;
compat_uptr_t region_params;
};
struct msm_actuator_params_t32 {
enum actuator_type act_type;
uint8_t reg_tbl_size;
uint16_t data_size;
uint16_t init_setting_size;
uint32_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_actuator_addr_type i2c_addr_type;
enum msm_actuator_data_type i2c_data_type;
compat_uptr_t reg_tbl_params;
compat_uptr_t init_settings;
struct park_lens_data_t park_lens;
};
struct msm_actuator_set_info_t32 {
struct msm_actuator_params_t32 actuator_params;
struct msm_actuator_tuning_params_t32 af_tuning_params;
};
struct sensor_init_cfg_data32 {
enum msm_sensor_init_cfg_type_t cfgtype;
struct msm_sensor_info_t probed_info;
char entity_name[MAX_SENSOR_NAME];
union {
compat_uptr_t setting;
} cfg;
};
struct msm_actuator_move_params_t32 {
int8_t dir;
int8_t sign_dir;
int16_t dest_step_pos;
int32_t num_steps;
uint16_t curr_lens_pos;
compat_uptr_t ringing_params;
};
struct msm_actuator_cfg_data32 {
int cfgtype;
uint8_t is_af_supported;
union {
struct msm_actuator_move_params_t32 move;
struct msm_actuator_set_info_t32 set_info;
struct msm_actuator_get_info_t get_info;
struct msm_actuator_set_position_t setpos;
enum af_camera_name cam_name;
} cfg;
};
struct csiphy_cfg_data32 {
enum csiphy_cfg_type_t cfgtype;
union {
compat_uptr_t csiphy_params;
compat_uptr_t csi_lane_params;
} cfg;
};
struct sensorb_cfg_data32 {
int cfgtype;
union {
struct msm_sensor_info_t sensor_info;
struct msm_sensor_init_params sensor_init_params;
compat_uptr_t setting;
struct msm_sensor_i2c_sync_params sensor_i2c_sync_params;
} cfg;
};
struct msm_ois_params_t32 {
uint16_t data_size;
uint16_t setting_size;
uint32_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type i2c_addr_type;
enum msm_camera_i2c_data_type i2c_data_type;
compat_uptr_t settings;
};
struct msm_ois_set_info_t32 {
struct msm_ois_params_t32 ois_params;
};
struct msm_ois_cfg_data32 {
int cfgtype;
union {
struct msm_ois_set_info_t32 set_info;
compat_uptr_t settings;
} cfg;
};
struct msm_flash_init_info_t32 {
enum msm_flash_driver_type flash_driver_type;
uint32_t slave_addr;
enum i2c_freq_mode_t i2c_freq_mode;
compat_uptr_t power_setting_array;
compat_uptr_t settings;
};
struct msm_flash_cfg_data_t32 {
enum msm_flash_cfg_type_t cfg_type;
int32_t flash_current[MAX_LED_TRIGGERS];
int32_t flash_duration[MAX_LED_TRIGGERS];
union {
compat_uptr_t flash_init_info;
compat_uptr_t settings;
} cfg;
};
#define VIDIOC_MSM_ACTUATOR_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data32)
#define VIDIOC_MSM_SENSOR_INIT_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data32)
#define VIDIOC_MSM_CSIPHY_IO_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data32)
#define VIDIOC_MSM_SENSOR_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data32)
#define VIDIOC_MSM_EEPROM_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data32)
#define VIDIOC_MSM_OIS_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data32)
#define VIDIOC_MSM_CSID_IO_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data32)
#define VIDIOC_MSM_FLASH_CFG32 \
_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t32)
#endif
#endif /* __LINUX_MSM_CAM_SENSOR_H */

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#ifndef __LINUX_MSM_CAMSENSOR_SDK_H
#define __LINUX_MSM_CAMSENSOR_SDK_H
#define KVERSION 0x1
#define MAX_POWER_CONFIG 12
#define GPIO_OUT_LOW (0 << 1)
#define GPIO_OUT_HIGH (1 << 1)
#define CSI_EMBED_DATA 0x12
#define CSI_RESERVED_DATA_0 0x13
#define CSI_YUV422_8 0x1E
#define CSI_RAW8 0x2A
#define CSI_RAW10 0x2B
#define CSI_RAW12 0x2C
#define CSI_DECODE_6BIT 0
#define CSI_DECODE_8BIT 1
#define CSI_DECODE_10BIT 2
#define CSI_DECODE_12BIT 3
#define CSI_DECODE_DPCM_10_8_10 5
#define MAX_CID 16
#define I2C_SEQ_REG_DATA_MAX 1024
#define I2C_REG_DATA_MAX (8*1024)
#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */
#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
/* 14 BGBG.. GRGR.. */
#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
/* 14 GBGB.. RGRG.. */
#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
/* 14 GRGR.. BGBG.. */
#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
/* 14 RGRG.. GBGB.. */
#define MAX_ACTUATOR_REG_TBL_SIZE 8
#define MAX_ACTUATOR_REGION 5
#define NUM_ACTUATOR_DIR 2
#define MAX_ACTUATOR_SCENARIO 8
#define MAX_ACT_MOD_NAME_SIZE 32
#define MAX_ACT_NAME_SIZE 32
#define MAX_ACTUATOR_INIT_SET 120
#define MAX_I2C_REG_SET 12
#define MAX_LED_TRIGGERS 3
#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80
#define MSM_EEPROM_MAX_MEM_MAP_CNT 8
enum msm_sensor_camera_id_t {
CAMERA_0,
CAMERA_1,
CAMERA_2,
CAMERA_3,
MAX_CAMERAS,
};
enum i2c_freq_mode_t {
I2C_STANDARD_MODE,
I2C_FAST_MODE,
I2C_CUSTOM_MODE,
I2C_FAST_PLUS_MODE,
I2C_MAX_MODES,
};
enum camb_position_t {
BACK_CAMERA_B,
FRONT_CAMERA_B,
AUX_CAMERA_B = 0x100,
INVALID_CAMERA_B,
};
enum msm_sensor_power_seq_type_t {
SENSOR_CLK,
SENSOR_GPIO,
SENSOR_VREG,
SENSOR_I2C_MUX,
SENSOR_I2C,
};
enum msm_camera_i2c_reg_addr_type {
MSM_CAMERA_I2C_BYTE_ADDR = 1,
MSM_CAMERA_I2C_WORD_ADDR,
MSM_CAMERA_I2C_3B_ADDR,
MSM_CAMERA_I2C_ADDR_TYPE_MAX,
};
enum msm_camera_i2c_data_type {
MSM_CAMERA_I2C_BYTE_DATA = 1,
MSM_CAMERA_I2C_WORD_DATA,
MSM_CAMERA_I2C_DWORD_DATA,
MSM_CAMERA_I2C_SET_BYTE_MASK,
MSM_CAMERA_I2C_UNSET_BYTE_MASK,
MSM_CAMERA_I2C_SET_WORD_MASK,
MSM_CAMERA_I2C_UNSET_WORD_MASK,
MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,
MSM_CAMERA_I2C_SEQ_DATA,
MSM_CAMERA_I2C_DATA_TYPE_MAX,
};
enum msm_sensor_power_seq_gpio_t {
SENSOR_GPIO_RESET,
SENSOR_GPIO_STANDBY,
SENSOR_GPIO_AF_PWDM,
SENSOR_GPIO_VIO,
SENSOR_GPIO_VANA,
SENSOR_GPIO_VDIG,
SENSOR_GPIO_VAF,
SENSOR_GPIO_FL_EN,
SENSOR_GPIO_FL_NOW,
SENSOR_GPIO_FL_RESET,
SENSOR_GPIO_CUSTOM1,
SENSOR_GPIO_CUSTOM2,
SENSOR_GPIO_MAX,
};
enum msm_camera_vreg_name_t {
CAM_VDIG,
CAM_VIO,
CAM_VANA,
CAM_VAF,
CAM_V_CUSTOM1,
CAM_V_CUSTOM2,
CAM_VREG_MAX,
};
enum msm_sensor_clk_type_t {
SENSOR_CAM_MCLK,
SENSOR_CAM_CLK,
SENSOR_CAM_CLK_MAX,
};
enum camerab_mode_t {
CAMERA_MODE_2D_B = (1<<0),
CAMERA_MODE_3D_B = (1<<1),
CAMERA_MODE_INVALID = (1<<2),
};
enum msm_actuator_data_type {
MSM_ACTUATOR_BYTE_DATA = 1,
MSM_ACTUATOR_WORD_DATA,
};
enum msm_actuator_addr_type {
MSM_ACTUATOR_BYTE_ADDR = 1,
MSM_ACTUATOR_WORD_ADDR,
};
enum msm_actuator_write_type {
MSM_ACTUATOR_WRITE_HW_DAMP,
MSM_ACTUATOR_WRITE_DAC,
MSM_ACTUATOR_WRITE,
MSM_ACTUATOR_WRITE_DIR_REG,
MSM_ACTUATOR_POLL,
MSM_ACTUATOR_READ_WRITE,
};
enum msm_actuator_i2c_operation {
MSM_ACT_WRITE = 0,
MSM_ACT_POLL,
};
enum actuator_type {
ACTUATOR_VCM,
ACTUATOR_PIEZO,
ACTUATOR_HVCM,
ACTUATOR_BIVCM,
};
enum msm_flash_driver_type {
FLASH_DRIVER_PMIC,
FLASH_DRIVER_I2C,
FLASH_DRIVER_GPIO,
FLASH_DRIVER_DEFAULT
};
enum msm_flash_cfg_type_t {
CFG_FLASH_INIT,
CFG_FLASH_RELEASE,
CFG_FLASH_OFF,
CFG_FLASH_LOW,
CFG_FLASH_HIGH,
};
enum msm_sensor_output_format_t {
MSM_SENSOR_BAYER,
MSM_SENSOR_YCBCR,
MSM_SENSOR_META,
};
struct msm_sensor_power_setting {
enum msm_sensor_power_seq_type_t seq_type;
unsigned short seq_val;
long config_val;
unsigned short delay;
void *data[10];
};
struct msm_sensor_power_setting_array {
struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG];
struct msm_sensor_power_setting *power_setting;
unsigned short size;
struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG];
struct msm_sensor_power_setting *power_down_setting;
unsigned short size_down;
};
enum msm_camera_i2c_operation {
MSM_CAM_WRITE = 0,
MSM_CAM_POLL,
MSM_CAM_READ,
};
struct msm_sensor_i2c_sync_params {
unsigned int cid;
int csid;
unsigned short line;
unsigned short delay;
};
struct msm_camera_reg_settings_t {
uint16_t reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
uint16_t reg_data;
enum msm_camera_i2c_data_type data_type;
enum msm_camera_i2c_operation i2c_operation;
uint16_t delay;
};
struct msm_eeprom_mem_map_t {
int slave_addr;
struct msm_camera_reg_settings_t
mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE];
int memory_map_size;
};
struct msm_eeprom_memory_map_array {
struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT];
uint32_t msm_size_of_max_mappings;
};
struct msm_sensor_init_params {
/* mask of modes supported: 2D, 3D */
int modes_supported;
/* sensor position: front, back */
enum camb_position_t position;
/* sensor mount angle */
unsigned int sensor_mount_angle;
};
struct msm_sensor_id_info_t {
unsigned short sensor_id_reg_addr;
unsigned short sensor_id;
unsigned short sensor_id_mask;
// added in LeEco
unsigned char module_id;
unsigned char vcm_id;
};
struct msm_camera_sensor_slave_info {
char sensor_name[32];
char eeprom_name[32];
char actuator_name[32];
char ois_name[32];
char flash_name[32];
enum msm_sensor_camera_id_t camera_id;
unsigned short slave_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type addr_type;
struct msm_sensor_id_info_t sensor_id_info;
struct msm_sensor_power_setting_array power_setting_array;
unsigned char is_init_params_valid;
struct msm_sensor_init_params sensor_init_params;
enum msm_sensor_output_format_t output_format;
};
struct msm_camera_i2c_reg_array {
unsigned short reg_addr;
unsigned short reg_data;
unsigned int delay;
};
struct msm_camera_i2c_reg_setting {
struct msm_camera_i2c_reg_array *reg_setting;
unsigned short size;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
unsigned short delay;
};
struct msm_camera_csid_vc_cfg {
unsigned char cid;
unsigned char dt;
unsigned char decode_format;
};
struct msm_camera_csid_lut_params {
unsigned char num_cid;
struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];
struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID];
};
struct msm_camera_csid_params {
unsigned char lane_cnt;
unsigned short lane_assign;
unsigned char phy_sel;
unsigned int csi_clk;
struct msm_camera_csid_lut_params lut_params;
unsigned char csi_3p_sel;
};
struct msm_camera_csid_testmode_parms {
unsigned int num_bytes_per_line;
unsigned int num_lines;
unsigned int h_blanking_count;
unsigned int v_blanking_count;
unsigned int payload_mode;
};
struct msm_camera_csiphy_params {
unsigned char lane_cnt;
unsigned char settle_cnt;
unsigned short lane_mask;
unsigned char combo_mode;
unsigned char csid_core;
unsigned int csiphy_clk;
unsigned char csi_3phase;
};
struct msm_camera_i2c_seq_reg_array {
unsigned short reg_addr;
unsigned char reg_data[I2C_SEQ_REG_DATA_MAX];
unsigned short reg_data_size;
};
struct msm_camera_i2c_seq_reg_setting {
struct msm_camera_i2c_seq_reg_array *reg_setting;
unsigned short size;
enum msm_camera_i2c_reg_addr_type addr_type;
unsigned short delay;
};
struct msm_actuator_reg_params_t {
enum msm_actuator_write_type reg_write_type;
unsigned int hw_mask;
unsigned short reg_addr;
unsigned short hw_shift;
unsigned short data_shift;
unsigned short data_type;
unsigned short addr_type;
unsigned short reg_data;
unsigned short delay;
};
struct damping_params_t {
unsigned int damping_step;
unsigned int damping_delay;
unsigned int hw_params;
};
struct region_params_t {
/* [0] = ForwardDirection Macro boundary
[1] = ReverseDirection Inf boundary
*/
unsigned short step_bound[2];
unsigned short code_per_step;
/* qvalue for converting float type numbers to integer format */
unsigned int qvalue;
};
struct reg_settings_t {
unsigned short reg_addr;
enum msm_actuator_addr_type addr_type;
unsigned short reg_data;
enum msm_actuator_data_type data_type;
enum msm_actuator_i2c_operation i2c_operation;
unsigned int delay;
};
struct msm_camera_i2c_reg_setting_array {
struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET];
unsigned short size;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
unsigned short delay;
};
#endif /* __LINUX_MSM_CAM_SENSOR_H */

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#ifndef _UAPI_MSM_ION_H
#define _UAPI_MSM_ION_H
#include <linux/ion.h>
enum msm_ion_heap_types {
ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1,
ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START,
ION_HEAP_TYPE_SYSTEM_SECURE,
ION_HEAP_TYPE_HYP_CMA,
/*
* if you add a heap type here you should also add it to
* heap_types_info[] in msm_ion.c
*/
};
/**
* These are the only ids that should be used for Ion heap ids.
* The ids listed are the order in which allocation will be attempted
* if specified. Don't swap the order of heap ids unless you know what
* you are doing!
* Id's are spaced by purpose to allow new Id's to be inserted in-between (for
* possible fallbacks)
*/
enum ion_heap_ids {
INVALID_HEAP_ID = -1,
ION_CP_MM_HEAP_ID = 8,
ION_SECURE_HEAP_ID = 9,
ION_SECURE_DISPLAY_HEAP_ID = 10,
ION_CP_MFC_HEAP_ID = 12,
ION_CP_WB_HEAP_ID = 16, /* 8660 only */
ION_CAMERA_HEAP_ID = 20, /* 8660 only */
ION_SYSTEM_CONTIG_HEAP_ID = 21,
ION_ADSP_HEAP_ID = 22,
ION_PIL1_HEAP_ID = 23, /* Currently used for other PIL images */
ION_SF_HEAP_ID = 24,
ION_SYSTEM_HEAP_ID = 25,
ION_PIL2_HEAP_ID = 26, /* Currently used for modem firmware images */
ION_QSECOM_HEAP_ID = 27,
ION_AUDIO_HEAP_ID = 28,
ION_MM_FIRMWARE_HEAP_ID = 29,
ION_HEAP_ID_RESERVED = 31 /** Bit reserved for ION_FLAG_SECURE flag */
};
/*
* The IOMMU heap is deprecated! Here are some aliases for backwards
* compatibility:
*/
#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID
#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM
enum ion_fixed_position {
NOT_FIXED,
FIXED_LOW,
FIXED_MIDDLE,
FIXED_HIGH,
};
enum cp_mem_usage {
VIDEO_BITSTREAM = 0x1,
VIDEO_PIXEL = 0x2,
VIDEO_NONPIXEL = 0x3,
DISPLAY_SECURE_CP_USAGE = 0x4,
CAMERA_SECURE_CP_USAGE = 0x5,
MAX_USAGE = 0x6,
UNKNOWN = 0x7FFFFFFF,
};
/**
* Flags to be used when allocating from the secure heap for
* content protection
*/
#define ION_FLAG_CP_TOUCH (1 << 17)
#define ION_FLAG_CP_BITSTREAM (1 << 18)
#define ION_FLAG_CP_PIXEL (1 << 19)
#define ION_FLAG_CP_NON_PIXEL (1 << 20)
#define ION_FLAG_CP_CAMERA (1 << 21)
#define ION_FLAG_CP_HLOS (1 << 22)
#define ION_FLAG_CP_HLOS_FREE (1 << 23)
#define ION_FLAG_CP_SEC_DISPLAY (1 << 25)
#define ION_FLAG_CP_APP (1 << 26)
/**
* Flag to allow non continguous allocation of memory from secure
* heap
*/
#define ION_FLAG_ALLOW_NON_CONTIG (1 << 24)
/**
* Flag to use when allocating to indicate that a heap is secure.
*/
#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED)
/**
* Flag for clients to force contiguous memort allocation
*
* Use of this flag is carefully monitored!
*/
#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30)
/*
* Used in conjunction with heap which pool memory to force an allocation
* to come from the page allocator directly instead of from the pool allocation
*/
#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16)
#define ION_FLAG_POOL_PREFETCH (1 << 27)
/**
* Deprecated! Please use the corresponding ION_FLAG_*
*/
#define ION_SECURE ION_FLAG_SECURE
#define ION_FORCE_CONTIGUOUS ION_FLAG_FORCE_CONTIGUOUS
/**
* Macro should be used with ion_heap_ids defined above.
*/
#define ION_HEAP(bit) (1 << (bit))
#define ION_ADSP_HEAP_NAME "adsp"
#define ION_SYSTEM_HEAP_NAME "system"
#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME
#define ION_KMALLOC_HEAP_NAME "kmalloc"
#define ION_AUDIO_HEAP_NAME "audio"
#define ION_SF_HEAP_NAME "sf"
#define ION_MM_HEAP_NAME "mm"
#define ION_CAMERA_HEAP_NAME "camera_preview"
#define ION_IOMMU_HEAP_NAME "iommu"
#define ION_MFC_HEAP_NAME "mfc"
#define ION_WB_HEAP_NAME "wb"
#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw"
#define ION_PIL1_HEAP_NAME "pil_1"
#define ION_PIL2_HEAP_NAME "pil_2"
#define ION_QSECOM_HEAP_NAME "qsecom"
#define ION_SECURE_HEAP_NAME "secure_heap"
#define ION_SECURE_DISPLAY_HEAP_NAME "secure_display"
#define ION_SET_CACHED(__cache) (__cache | ION_FLAG_CACHED)
#define ION_SET_UNCACHED(__cache) (__cache & ~ION_FLAG_CACHED)
#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED)
/* struct ion_flush_data - data passed to ion for flushing caches
*
* @handle: handle with data to flush
* @fd: fd to flush
* @vaddr: userspace virtual address mapped with mmap
* @offset: offset into the handle to flush
* @length: length of handle to flush
*
* Performs cache operations on the handle. If p is the start address
* of the handle, p + offset through p + offset + length will have
* the cache operations performed
*/
struct ion_flush_data {
ion_user_handle_t handle;
int fd;
void *vaddr;
unsigned int offset;
unsigned int length;
};
struct ion_prefetch_regions {
unsigned int vmid;
size_t *sizes;
unsigned int nr_sizes;
};
struct ion_prefetch_data {
int heap_id;
unsigned long len;
/* Is unsigned long bad? 32bit compiler vs 64 bit compiler*/
struct ion_prefetch_regions *regions;
unsigned int nr_regions;
};
#define ION_IOC_MSM_MAGIC 'M'
/**
* DOC: ION_IOC_CLEAN_CACHES - clean the caches
*
* Clean the caches of the handle specified.
*/
#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, \
struct ion_flush_data)
/**
* DOC: ION_IOC_INV_CACHES - invalidate the caches
*
* Invalidate the caches of the handle specified.
*/
#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, \
struct ion_flush_data)
/**
* DOC: ION_IOC_CLEAN_INV_CACHES - clean and invalidate the caches
*
* Clean and invalidate the caches of the handle specified.
*/
#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \
struct ion_flush_data)
#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, \
struct ion_prefetch_data)
#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, \
struct ion_prefetch_data)
#endif

1449
third_party/linux/include/msm_kgsl.h vendored Normal file
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819
third_party/linux/include/msm_media_info.h vendored Normal file
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#ifndef __MEDIA_INFO_H__
#define __MEDIA_INFO_H__
#ifndef MSM_MEDIA_ALIGN
#define MSM_MEDIA_ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1)))
#endif
#ifndef MSM_MEDIA_ROUNDUP
#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r))
#endif
#ifndef MSM_MEDIA_MAX
#define MSM_MEDIA_MAX(__a, __b) ((__a) > (__b)?(__a):(__b))
#endif
enum color_fmts {
/* Venus NV12:
* YUV 4:2:0 image with a plane of 8 bit Y samples followed
* by an interleaved U/V plane containing 8 bit 2x2 subsampled
* colour difference samples.
*
* <-------- Y/UV_Stride -------->
* <------- Width ------->
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
* U V U V U V U V U V U V . . . . ^
* U V U V U V U V U V U V . . . . |
* U V U V U V U V U V U V . . . . |
* U V U V U V U V U V U V . . . . UV_Scanlines
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
* . . . . . . . . . . . . . . . . --> Buffer size alignment
*
* Y_Stride : Width aligned to 128
* UV_Stride : Width aligned to 128
* Y_Scanlines: Height aligned to 32
* UV_Scanlines: Height/2 aligned to 16
* Extradata: Arbitrary (software-imposed) padding
* Total size = align((Y_Stride * Y_Scanlines
* + UV_Stride * UV_Scanlines
* + max(Extradata, Y_Stride * 8), 4096)
*/
COLOR_FMT_NV12,
/* Venus NV21:
* YUV 4:2:0 image with a plane of 8 bit Y samples followed
* by an interleaved V/U plane containing 8 bit 2x2 subsampled
* colour difference samples.
*
* <-------- Y/UV_Stride -------->
* <------- Width ------->
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
* V U V U V U V U V U V U . . . . ^
* V U V U V U V U V U V U . . . . |
* V U V U V U V U V U V U . . . . |
* V U V U V U V U V U V U . . . . UV_Scanlines
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
* . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment
*
* Y_Stride : Width aligned to 128
* UV_Stride : Width aligned to 128
* Y_Scanlines: Height aligned to 32
* UV_Scanlines: Height/2 aligned to 16
* Extradata: Arbitrary (software-imposed) padding
* Total size = align((Y_Stride * Y_Scanlines
* + UV_Stride * UV_Scanlines
* + max(Extradata, Y_Stride * 8), 4096)
*/
COLOR_FMT_NV21,
/* Venus NV12_MVTB:
* Two YUV 4:2:0 images/views one after the other
* in a top-bottom layout, same as NV12
* with a plane of 8 bit Y samples followed
* by an interleaved U/V plane containing 8 bit 2x2 subsampled
* colour difference samples.
*
*
* <-------- Y/UV_Stride -------->
* <------- Width ------->
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | |
* . . . . . . . . . . . . . . . . | View_1
* . . . . . . . . . . . . . . . . | |
* . . . . . . . . . . . . . . . . | |
* . . . . . . . . . . . . . . . . V |
* U V U V U V U V U V U V . . . . ^ |
* U V U V U V U V U V U V . . . . | |
* U V U V U V U V U V U V . . . . | |
* U V U V U V U V U V U V . . . . UV_Scanlines |
* . . . . . . . . . . . . . . . . | |
* . . . . . . . . . . . . . . . . V V
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | |
* . . . . . . . . . . . . . . . . | View_2
* . . . . . . . . . . . . . . . . | |
* . . . . . . . . . . . . . . . . | |
* . . . . . . . . . . . . . . . . V |
* U V U V U V U V U V U V . . . . ^ |
* U V U V U V U V U V U V . . . . | |
* U V U V U V U V U V U V . . . . | |
* U V U V U V U V U V U V . . . . UV_Scanlines |
* . . . . . . . . . . . . . . . . | |
* . . . . . . . . . . . . . . . . V V
* . . . . . . . . . . . . . . . . --> Buffer size alignment
*
* Y_Stride : Width aligned to 128
* UV_Stride : Width aligned to 128
* Y_Scanlines: Height aligned to 32
* UV_Scanlines: Height/2 aligned to 16
* View_1 begin at: 0 (zero)
* View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines
* Extradata: Arbitrary (software-imposed) padding
* Total size = align((2*(Y_Stride * Y_Scanlines)
* + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096)
*/
COLOR_FMT_NV12_MVTB,
/* Venus NV12 UBWC:
* Compressed Macro-tile format for NV12.
* Contains 4 planes in the following order -
* (A) Y_Meta_Plane
* (B) Y_UBWC_Plane
* (C) UV_Meta_Plane
* (D) UV_UBWC_Plane
*
* Y_Meta_Plane consists of meta information to decode compressed
* tile data in Y_UBWC_Plane.
* Y_UBWC_Plane consists of Y data in compressed macro-tile format.
* UBWC decoder block will use the Y_Meta_Plane data together with
* Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples.
*
* UV_Meta_Plane consists of meta information to decode compressed
* tile data in UV_UBWC_Plane.
* UV_UBWC_Plane consists of UV data in compressed macro-tile format.
* UBWC decoder block will use UV_Meta_Plane data together with
* UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2
* subsampled color difference samples.
*
* Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
* and randomly accessible. There is no dependency between tiles.
*
* <----- Y_Meta_Stride ---->
* <-------- Width ------>
* M M M M M M M M M M M M . . ^ ^
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . Height |
* M M M M M M M M M M M M . . | Meta_Y_Scanlines
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . V |
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* . . . . . . . . . . . . . . V
* <--Compressed tile Y Stride--->
* <------- Width ------->
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* . . . . . . . . . . . . . . . . V
* <----- UV_Meta_Stride ---->
* M M M M M M M M M M M M . . ^
* M M M M M M M M M M M M . . |
* M M M M M M M M M M M M . . |
* M M M M M M M M M M M M . . M_UV_Scanlines
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . V
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* <--Compressed tile UV Stride--->
* U* V* U* V* U* V* U* V* . . . . ^
* U* V* U* V* U* V* U* V* . . . . |
* U* V* U* V* U* V* U* V* . . . . |
* U* V* U* V* U* V* U* V* . . . . UV_Scanlines
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
*
* Y_Stride = align(Width, 128)
* UV_Stride = align(Width, 128)
* Y_Scanlines = align(Height, 32)
* UV_Scanlines = align(Height/2, 16)
* Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096)
* UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096)
* Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
* Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)
* Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)
* UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
* UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)
* UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)
* Extradata = 8k
*
* Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size +
* Y_Meta_Plane_size + UV_Meta_Plane_size
* + max(Extradata, Y_Stride * 48), 4096)
*/
COLOR_FMT_NV12_UBWC,
/* Venus NV12 10-bit UBWC:
* Compressed Macro-tile format for NV12.
* Contains 4 planes in the following order -
* (A) Y_Meta_Plane
* (B) Y_UBWC_Plane
* (C) UV_Meta_Plane
* (D) UV_UBWC_Plane
*
* Y_Meta_Plane consists of meta information to decode compressed
* tile data in Y_UBWC_Plane.
* Y_UBWC_Plane consists of Y data in compressed macro-tile format.
* UBWC decoder block will use the Y_Meta_Plane data together with
* Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples.
*
* UV_Meta_Plane consists of meta information to decode compressed
* tile data in UV_UBWC_Plane.
* UV_UBWC_Plane consists of UV data in compressed macro-tile format.
* UBWC decoder block will use UV_Meta_Plane data together with
* UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2
* subsampled color difference samples.
*
* Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
* and randomly accessible. There is no dependency between tiles.
*
* <----- Y_Meta_Stride ----->
* <-------- Width ------>
* M M M M M M M M M M M M . . ^ ^
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . Height |
* M M M M M M M M M M M M . . | Meta_Y_Scanlines
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . V |
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* . . . . . . . . . . . . . . V
* <--Compressed tile Y Stride--->
* <------- Width ------->
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* . . . . . . . . . . . . . . . . V
* <----- UV_Meta_Stride ---->
* M M M M M M M M M M M M . . ^
* M M M M M M M M M M M M . . |
* M M M M M M M M M M M M . . |
* M M M M M M M M M M M M . . M_UV_Scanlines
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . V
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* <--Compressed tile UV Stride--->
* U* V* U* V* U* V* U* V* . . . . ^
* U* V* U* V* U* V* U* V* . . . . |
* U* V* U* V* U* V* U* V* . . . . |
* U* V* U* V* U* V* U* V* . . . . UV_Scanlines
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
*
*
* Y_Stride = align(Width * 4/3, 128)
* UV_Stride = align(Width * 4/3, 128)
* Y_Scanlines = align(Height, 32)
* UV_Scanlines = align(Height/2, 16)
* Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096)
* UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096)
* Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
* Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)
* Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)
* UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
* UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)
* UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)
* Extradata = 8k
*
* Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size +
* Y_Meta_Plane_size + UV_Meta_Plane_size
* + max(Extradata, Y_Stride * 48), 4096)
*/
COLOR_FMT_NV12_BPP10_UBWC,
/* Venus RGBA8888 format:
* Contains 1 plane in the following order -
* (A) RGBA plane
*
* <-------- RGB_Stride -------->
* <------- Width ------->
* R R R R R R R R R R R R . . . . ^ ^
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . Height |
* R R R R R R R R R R R R . . . . | RGB_Scanlines
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . V |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . V
*
* RGB_Stride = align(Width * 4, 128)
* RGB_Scanlines = align(Height, 32)
* RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)
* Extradata = 8k
*
* Total size = align(RGB_Plane_size + Extradata, 4096)
*/
COLOR_FMT_RGBA8888,
/* Venus RGBA8888 UBWC format:
* Contains 2 planes in the following order -
* (A) Meta plane
* (B) RGBA plane
*
* <--- RGB_Meta_Stride ---->
* <-------- Width ------>
* M M M M M M M M M M M M . . ^ ^
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . Height |
* M M M M M M M M M M M M . . | Meta_RGB_Scanlines
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . | |
* M M M M M M M M M M M M . . V |
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* . . . . . . . . . . . . . . V
* <-------- RGB_Stride -------->
* <------- Width ------->
* R R R R R R R R R R R R . . . . ^ ^
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . Height |
* R R R R R R R R R R R R . . . . | RGB_Scanlines
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . | |
* R R R R R R R R R R R R . . . . V |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . |
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
* . . . . . . . . . . . . . . . . V
*
* RGB_Stride = align(Width * 4, 128)
* RGB_Scanlines = align(Height, 32)
* RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)
* RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64)
* RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16)
* RGB_Meta_Plane_size = align(RGB_Meta_Stride *
* RGB_Meta_Scanlines, 4096)
* Extradata = 8k
*
* Total size = align(RGB_Meta_Plane_size + RGB_Plane_size +
* Extradata, 4096)
*/
COLOR_FMT_RGBA8888_UBWC,
};
static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height)
{
(void)height;
(void)width;
/*
* In the future, calculate the size based on the w/h but just
* hardcode it for now since 16K satisfies all current usecases.
*/
return 16 * 1024;
}
static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width)
{
unsigned int alignment, stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
case COLOR_FMT_NV12_MVTB:
case COLOR_FMT_NV12_UBWC:
alignment = 128;
stride = MSM_MEDIA_ALIGN(width, alignment);
break;
case COLOR_FMT_NV12_BPP10_UBWC:
alignment = 256;
stride = MSM_MEDIA_ALIGN(width, 192);
stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment);
break;
default:
break;
}
invalid_input:
return stride;
}
static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width)
{
unsigned int alignment, stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
case COLOR_FMT_NV12_MVTB:
case COLOR_FMT_NV12_UBWC:
alignment = 128;
stride = MSM_MEDIA_ALIGN(width, alignment);
break;
case COLOR_FMT_NV12_BPP10_UBWC:
alignment = 256;
stride = MSM_MEDIA_ALIGN(width, 192);
stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment);
break;
default:
break;
}
invalid_input:
return stride;
}
static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height)
{
unsigned int alignment, sclines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
case COLOR_FMT_NV12_MVTB:
case COLOR_FMT_NV12_UBWC:
alignment = 32;
break;
case COLOR_FMT_NV12_BPP10_UBWC:
alignment = 16;
break;
default:
return 0;
}
sclines = MSM_MEDIA_ALIGN(height, alignment);
invalid_input:
return sclines;
}
static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height)
{
unsigned int alignment, sclines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
case COLOR_FMT_NV12_MVTB:
case COLOR_FMT_NV12_BPP10_UBWC:
alignment = 16;
break;
case COLOR_FMT_NV12_UBWC:
alignment = 32;
break;
default:
goto invalid_input;
}
sclines = MSM_MEDIA_ALIGN(height / 2, alignment);
invalid_input:
return sclines;
}
static inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width)
{
int y_tile_width = 0, y_meta_stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV12_UBWC:
y_tile_width = 32;
break;
case COLOR_FMT_NV12_BPP10_UBWC:
y_tile_width = 48;
break;
default:
goto invalid_input;
}
y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width);
y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64);
invalid_input:
return y_meta_stride;
}
static inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height)
{
int y_tile_height = 0, y_meta_scanlines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV12_UBWC:
y_tile_height = 8;
break;
case COLOR_FMT_NV12_BPP10_UBWC:
y_tile_height = 4;
break;
default:
goto invalid_input;
}
y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height);
y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16);
invalid_input:
return y_meta_scanlines;
}
static inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width)
{
int uv_tile_width = 0, uv_meta_stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV12_UBWC:
uv_tile_width = 16;
break;
case COLOR_FMT_NV12_BPP10_UBWC:
uv_tile_width = 24;
break;
default:
goto invalid_input;
}
uv_meta_stride = MSM_MEDIA_ROUNDUP(width / 2, uv_tile_width);
uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64);
invalid_input:
return uv_meta_stride;
}
static inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height)
{
int uv_tile_height = 0, uv_meta_scanlines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV12_UBWC:
uv_tile_height = 8;
break;
case COLOR_FMT_NV12_BPP10_UBWC:
uv_tile_height = 4;
break;
default:
goto invalid_input;
}
uv_meta_scanlines = MSM_MEDIA_ROUNDUP(height / 2, uv_tile_height);
uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16);
invalid_input:
return uv_meta_scanlines;
}
static inline unsigned int VENUS_RGB_STRIDE(int color_fmt, int width)
{
unsigned int alignment = 0, stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_RGBA8888:
alignment = 128;
break;
case COLOR_FMT_RGBA8888_UBWC:
alignment = 256;
break;
default:
goto invalid_input;
}
stride = MSM_MEDIA_ALIGN(width * 4, alignment);
invalid_input:
return stride;
}
static inline unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height)
{
unsigned int alignment = 0, scanlines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_RGBA8888:
alignment = 32;
break;
case COLOR_FMT_RGBA8888_UBWC:
alignment = 16;
break;
default:
goto invalid_input;
}
scanlines = MSM_MEDIA_ALIGN(height, alignment);
invalid_input:
return scanlines;
}
static inline unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width)
{
int rgb_tile_width = 0, rgb_meta_stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_RGBA8888_UBWC:
rgb_tile_width = 16;
break;
default:
goto invalid_input;
}
rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, rgb_tile_width);
rgb_meta_stride = MSM_MEDIA_ALIGN(rgb_meta_stride, 64);
invalid_input:
return rgb_meta_stride;
}
static inline unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height)
{
int rgb_tile_height = 0, rgb_meta_scanlines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_RGBA8888_UBWC:
rgb_tile_height = 4;
break;
default:
goto invalid_input;
}
rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, rgb_tile_height);
rgb_meta_scanlines = MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16);
invalid_input:
return rgb_meta_scanlines;
}
static inline unsigned int VENUS_BUFFER_SIZE(
int color_fmt, int width, int height)
{
const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height);
unsigned int uv_alignment = 0, size = 0;
unsigned int y_plane, uv_plane, y_stride,
uv_stride, y_sclines, uv_sclines;
unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0;
unsigned int y_meta_stride = 0, y_meta_scanlines = 0;
unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0;
unsigned int y_meta_plane = 0, uv_meta_plane = 0;
unsigned int rgb_stride = 0, rgb_scanlines = 0;
unsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane = 0;
unsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0;
if (!width || !height)
goto invalid_input;
y_stride = VENUS_Y_STRIDE(color_fmt, width);
uv_stride = VENUS_UV_STRIDE(color_fmt, width);
y_sclines = VENUS_Y_SCANLINES(color_fmt, height);
uv_sclines = VENUS_UV_SCANLINES(color_fmt, height);
rgb_stride = VENUS_RGB_STRIDE(color_fmt, width);
rgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height);
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
uv_alignment = 4096;
y_plane = y_stride * y_sclines;
uv_plane = uv_stride * uv_sclines + uv_alignment;
size = y_plane + uv_plane +
MSM_MEDIA_MAX(extra_size, 8 * y_stride);
size = MSM_MEDIA_ALIGN(size, 4096);
break;
case COLOR_FMT_NV12_MVTB:
uv_alignment = 4096;
y_plane = y_stride * y_sclines;
uv_plane = uv_stride * uv_sclines + uv_alignment;
size = y_plane + uv_plane;
size = 2 * size + extra_size;
size = MSM_MEDIA_ALIGN(size, 4096);
break;
case COLOR_FMT_NV12_UBWC:
case COLOR_FMT_NV12_BPP10_UBWC:
y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096);
uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096);
y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width);
y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height);
y_meta_plane = MSM_MEDIA_ALIGN(
y_meta_stride * y_meta_scanlines, 4096);
uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width);
uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height);
uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride *
uv_meta_scanlines, 4096);
size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane +
uv_meta_plane +
MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride);
size = MSM_MEDIA_ALIGN(size, 4096);
break;
case COLOR_FMT_RGBA8888:
rgb_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, 4096);
size = rgb_plane;
size = MSM_MEDIA_ALIGN(size, 4096);
break;
case COLOR_FMT_RGBA8888_UBWC:
rgb_ubwc_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines,
4096);
rgb_meta_stride = VENUS_RGB_META_STRIDE(color_fmt, width);
rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color_fmt,
height);
rgb_meta_plane = MSM_MEDIA_ALIGN(rgb_meta_stride *
rgb_meta_scanlines, 4096);
size = rgb_ubwc_plane + rgb_meta_plane;
size = MSM_MEDIA_ALIGN(size, 4096);
break;
default:
break;
}
invalid_input:
return size;
}
static inline unsigned int VENUS_VIEW2_OFFSET(
int color_fmt, int width, int height)
{
unsigned int offset = 0;
unsigned int y_plane, uv_plane, y_stride,
uv_stride, y_sclines, uv_sclines;
if (!width || !height)
goto invalid_input;
y_stride = VENUS_Y_STRIDE(color_fmt, width);
uv_stride = VENUS_UV_STRIDE(color_fmt, width);
y_sclines = VENUS_Y_SCANLINES(color_fmt, height);
uv_sclines = VENUS_UV_SCANLINES(color_fmt, height);
switch (color_fmt) {
case COLOR_FMT_NV12_MVTB:
y_plane = y_stride * y_sclines;
uv_plane = uv_stride * uv_sclines;
offset = y_plane + uv_plane;
break;
default:
break;
}
invalid_input:
return offset;
}
#endif

220
third_party/linux/include/msmb_camera.h vendored Normal file
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@@ -0,0 +1,220 @@
#ifndef __LINUX_MSMB_CAMERA_H
#define __LINUX_MSMB_CAMERA_H
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#define MSM_CAM_LOGSYNC_FILE_NAME "logsync"
#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera"
#define MSM_CAM_V4L2_IOCTL_NOTIFY \
_IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \
_IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_CMD_ACK \
_IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \
_IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG \
_IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data)
#ifdef CONFIG_COMPAT
#define MSM_CAM_V4L2_IOCTL_NOTIFY32 \
_IOW('V', BASE_VIDIOC_PRIVATE + 30, struct v4l2_event32)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_META32 \
_IOW('V', BASE_VIDIOC_PRIVATE + 31, struct v4l2_event32)
#define MSM_CAM_V4L2_IOCTL_CMD_ACK32 \
_IOW('V', BASE_VIDIOC_PRIVATE + 32, struct v4l2_event32)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR32 \
_IOW('V', BASE_VIDIOC_PRIVATE + 33, struct v4l2_event32)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG32 \
_IOW('V', BASE_VIDIOC_PRIVATE + 34, struct v4l2_event32)
#endif
#define QCAMERA_DEVICE_GROUP_ID 1
#define QCAMERA_VNODE_GROUP_ID 2
#define MSM_CAMERA_NAME "msm_camera"
#define MSM_CONFIGURATION_NAME "msm_config"
#define MSM_CAMERA_SUBDEV_CSIPHY 0
#define MSM_CAMERA_SUBDEV_CSID 1
#define MSM_CAMERA_SUBDEV_ISPIF 2
#define MSM_CAMERA_SUBDEV_VFE 3
#define MSM_CAMERA_SUBDEV_AXI 4
#define MSM_CAMERA_SUBDEV_VPE 5
#define MSM_CAMERA_SUBDEV_SENSOR 6
#define MSM_CAMERA_SUBDEV_ACTUATOR 7
#define MSM_CAMERA_SUBDEV_EEPROM 8
#define MSM_CAMERA_SUBDEV_CPP 9
#define MSM_CAMERA_SUBDEV_CCI 10
#define MSM_CAMERA_SUBDEV_LED_FLASH 11
#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12
#define MSM_CAMERA_SUBDEV_BUF_MNGR 13
#define MSM_CAMERA_SUBDEV_SENSOR_INIT 14
#define MSM_CAMERA_SUBDEV_OIS 15
#define MSM_CAMERA_SUBDEV_FLASH 16
#define MSM_CAMERA_SUBDEV_EXT 17
#define MSM_MAX_CAMERA_SENSORS 5
/* The below macro is defined to put an upper limit on maximum
* number of buffer requested per stream. In case of extremely
* large value for number of buffer due to data structure corruption
* we return error to avoid integer overflow. Group processing
* can have max of 9 groups of 8 bufs each. This value may be
* configured in future*/
#define MSM_CAMERA_MAX_STREAM_BUF 72
/* Max batch size of processing */
#define MSM_CAMERA_MAX_USER_BUFF_CNT 16
/* featur base */
#define MSM_CAMERA_FEATURE_BASE 0x00010000
#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1)
#define MSM_CAMERA_STATUS_BASE 0x00020000
#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1)
#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2)
/* event type */
#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000)
/* event id */
#define MSM_CAMERA_EVENT_MIN 0
#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1)
#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2)
#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3)
#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4)
#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5)
#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6)
#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7)
#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8)
/* data.command */
#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1)
#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2)
#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3)
#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4)
#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5)
#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6)
#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7)
#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8)
#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9)
#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10)
#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11)
#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12)
#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \
(V4L2_CID_PRIVATE_BASE + 13)
#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14)
#define MSM_CAMERA_PRIV_CMD_MAX 20
/* data.status - success */
#define MSM_CAMERA_CMD_SUCESS 0x00000001
#define MSM_CAMERA_BUF_MAP_SUCESS 0x00000002
/* data.status - error */
#define MSM_CAMERA_ERR_EVT_BASE 0x00010000
#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1)
#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2)
#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3)
/* The msm_v4l2_event_data structure should match the
* v4l2_event.u.data field.
* should not exceed 16 elements */
struct msm_v4l2_event_data {
/*word 0*/
unsigned int command;
/*word 1*/
unsigned int status;
/*word 2*/
unsigned int session_id;
/*word 3*/
unsigned int stream_id;
/*word 4*/
unsigned int map_op;
/*word 5*/
unsigned int map_buf_idx;
/*word 6*/
unsigned int notify;
/*word 7*/
unsigned int arg_value;
/*word 8*/
unsigned int ret_value;
/*word 9*/
unsigned int v4l2_event_type;
/*word 10*/
unsigned int v4l2_event_id;
/*word 11*/
unsigned int handle;
/*word 12*/
unsigned int nop6;
/*word 13*/
unsigned int nop7;
/*word 14*/
unsigned int nop8;
/*word 15*/
unsigned int nop9;
};
/* map to v4l2_format.fmt.raw_data */
struct msm_v4l2_format_data {
enum v4l2_buf_type type;
unsigned int width;
unsigned int height;
unsigned int pixelformat; /* FOURCC */
unsigned char num_planes;
unsigned int plane_sizes[VIDEO_MAX_PLANES];
};
/* MSM Four-character-code (FOURCC) */
#define msm_v4l2_fourcc(a, b, c, d)\
((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\
((__u32)(d) << 24))
/* Composite stats */
#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M')
/* AEC stats */
#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E')
/* AF stats */
#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F')
/* AWB stats */
#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B')
/* IHIST stats */
#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T')
/* Column count stats */
#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S')
/* Row count stats */
#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S')
/* Bayer Grid stats */
#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G')
/* Bayer focus stats */
#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F')
/* Bayer hist stats */
#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T')
enum smmu_attach_mode {
NON_SECURE_MODE = 0x01,
SECURE_MODE = 0x02,
MAX_PROTECTION_MODE = 0x03,
};
struct msm_camera_smmu_attach_type {
enum smmu_attach_mode attach;
};
struct msm_camera_user_buf_cont_t {
unsigned int buf_cnt;
unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT];
};
#endif /* __LINUX_MSMB_CAMERA_H */

880
third_party/linux/include/msmb_isp.h vendored Normal file
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@@ -0,0 +1,880 @@
#ifndef __MSMB_ISP__
#define __MSMB_ISP__
#include <linux/videodev2.h>
#define MAX_PLANES_PER_STREAM 3
#define MAX_NUM_STREAM 7
#define ISP_VERSION_47 47
#define ISP_VERSION_46 46
#define ISP_VERSION_44 44
#define ISP_VERSION_40 40
#define ISP_VERSION_32 32
#define ISP_NATIVE_BUF_BIT (0x10000 << 0)
#define ISP0_BIT (0x10000 << 1)
#define ISP1_BIT (0x10000 << 2)
#define ISP_META_CHANNEL_BIT (0x10000 << 3)
#define ISP_SCRATCH_BUF_BIT (0x10000 << 4)
#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
#define ISP_STATS_STREAM_BIT 0x80000000
struct msm_vfe_cfg_cmd_list;
enum ISP_START_PIXEL_PATTERN {
ISP_BAYER_RGRGRG,
ISP_BAYER_GRGRGR,
ISP_BAYER_BGBGBG,
ISP_BAYER_GBGBGB,
ISP_YUV_YCbYCr,
ISP_YUV_YCrYCb,
ISP_YUV_CbYCrY,
ISP_YUV_CrYCbY,
ISP_PIX_PATTERN_MAX
};
enum msm_vfe_plane_fmt {
Y_PLANE,
CB_PLANE,
CR_PLANE,
CRCB_PLANE,
CBCR_PLANE,
VFE_PLANE_FMT_MAX
};
enum msm_vfe_input_src {
VFE_PIX_0,
VFE_RAW_0,
VFE_RAW_1,
VFE_RAW_2,
VFE_SRC_MAX,
};
enum msm_vfe_axi_stream_src {
PIX_ENCODER,
PIX_VIEWFINDER,
PIX_VIDEO,
CAMIF_RAW,
IDEAL_RAW,
RDI_INTF_0,
RDI_INTF_1,
RDI_INTF_2,
VFE_AXI_SRC_MAX
};
enum msm_vfe_frame_skip_pattern {
NO_SKIP,
EVERY_2FRAME,
EVERY_3FRAME,
EVERY_4FRAME,
EVERY_5FRAME,
EVERY_6FRAME,
EVERY_7FRAME,
EVERY_8FRAME,
EVERY_16FRAME,
EVERY_32FRAME,
SKIP_ALL,
SKIP_RANGE,
MAX_SKIP,
};
/*
* Define an unused period. When this period is set it means that the stream is
* stopped(i.e the pattern is 0). We don't track the current pattern, just the
* period defines what the pattern is, if period is this then pattern is 0 else
* pattern is 1
*/
#define MSM_VFE_STREAM_STOP_PERIOD 15
enum msm_isp_stats_type {
MSM_ISP_STATS_AEC, /* legacy based AEC */
MSM_ISP_STATS_AF, /* legacy based AF */
MSM_ISP_STATS_AWB, /* legacy based AWB */
MSM_ISP_STATS_RS, /* legacy based RS */
MSM_ISP_STATS_CS, /* legacy based CS */
MSM_ISP_STATS_IHIST, /* legacy based HIST */
MSM_ISP_STATS_SKIN, /* legacy based SKIN */
MSM_ISP_STATS_BG, /* Bayer Grids */
MSM_ISP_STATS_BF, /* Bayer Focus */
MSM_ISP_STATS_BE, /* Bayer Exposure*/
MSM_ISP_STATS_BHIST, /* Bayer Hist */
MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */
MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */
MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
MSM_ISP_STATS_AEC_BG, /* AEC BG */
MSM_ISP_STATS_MAX /* MAX */
};
/*
* @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
* @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
* @skip_mode: skip pattern, if skip mode is range only then min/max is used
* @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
* @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
*/
struct msm_isp_sw_framskip {
uint32_t stats_type_mask;
uint32_t stream_src_mask;
enum msm_vfe_frame_skip_pattern skip_mode;
uint32_t min_frame_id;
uint32_t max_frame_id;
};
enum msm_vfe_testgen_color_pattern {
COLOR_BAR_8_COLOR,
UNICOLOR_WHITE,
UNICOLOR_YELLOW,
UNICOLOR_CYAN,
UNICOLOR_GREEN,
UNICOLOR_MAGENTA,
UNICOLOR_RED,
UNICOLOR_BLUE,
UNICOLOR_BLACK,
MAX_COLOR,
};
enum msm_vfe_camif_input {
CAMIF_DISABLED,
CAMIF_PAD_REG_INPUT,
CAMIF_MIDDI_INPUT,
CAMIF_MIPI_INPUT,
};
struct msm_vfe_fetch_engine_cfg {
uint32_t input_format;
uint32_t buf_width;
uint32_t buf_height;
uint32_t fetch_width;
uint32_t fetch_height;
uint32_t x_offset;
uint32_t y_offset;
uint32_t buf_stride;
};
enum msm_vfe_camif_output_format {
CAMIF_QCOM_RAW,
CAMIF_MIPI_RAW,
CAMIF_PLAIN_8,
CAMIF_PLAIN_16,
CAMIF_MAX_FORMAT,
};
/*
* Camif output general configuration
*/
struct msm_vfe_camif_subsample_cfg {
uint32_t irq_subsample_period;
uint32_t irq_subsample_pattern;
uint32_t sof_counter_step;
uint32_t pixel_skip;
uint32_t line_skip;
uint32_t first_line;
uint32_t last_line;
uint32_t first_pixel;
uint32_t last_pixel;
enum msm_vfe_camif_output_format output_format;
};
/*
* Camif frame and window configuration
*/
struct msm_vfe_camif_cfg {
uint32_t lines_per_frame;
uint32_t pixels_per_line;
uint32_t first_pixel;
uint32_t last_pixel;
uint32_t first_line;
uint32_t last_line;
uint32_t epoch_line0;
uint32_t epoch_line1;
uint32_t is_split;
enum msm_vfe_camif_input camif_input;
struct msm_vfe_camif_subsample_cfg subsample_cfg;
};
struct msm_vfe_testgen_cfg {
uint32_t lines_per_frame;
uint32_t pixels_per_line;
uint32_t v_blank;
uint32_t h_blank;
enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
uint32_t rotate_period;
enum msm_vfe_testgen_color_pattern color_bar_pattern;
uint32_t burst_num_frame;
};
enum msm_vfe_inputmux {
CAMIF,
TESTGEN,
EXTERNAL_READ,
};
enum msm_vfe_stats_composite_group {
STATS_COMPOSITE_GRP_NONE,
STATS_COMPOSITE_GRP_1,
STATS_COMPOSITE_GRP_2,
STATS_COMPOSITE_GRP_MAX,
};
enum msm_vfe_hvx_streaming_cmd {
HVX_DISABLE,
HVX_ONE_WAY,
HVX_ROUND_TRIP
};
struct msm_vfe_pix_cfg {
struct msm_vfe_camif_cfg camif_cfg;
struct msm_vfe_testgen_cfg testgen_cfg;
struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
enum msm_vfe_inputmux input_mux;
enum ISP_START_PIXEL_PATTERN pixel_pattern;
uint32_t input_format;
enum msm_vfe_hvx_streaming_cmd hvx_cmd;
uint32_t is_split;
};
struct msm_vfe_rdi_cfg {
uint8_t cid;
uint8_t frame_based;
};
struct msm_vfe_input_cfg {
union {
struct msm_vfe_pix_cfg pix_cfg;
struct msm_vfe_rdi_cfg rdi_cfg;
} d;
enum msm_vfe_input_src input_src;
uint32_t input_pix_clk;
};
struct msm_vfe_fetch_eng_start {
uint32_t session_id;
uint32_t stream_id;
uint32_t buf_idx;
uint8_t offline_mode;
uint32_t fd;
uint32_t buf_addr;
uint32_t frame_id;
};
struct msm_vfe_axi_plane_cfg {
uint32_t output_width; /*Include padding*/
uint32_t output_height;
uint32_t output_stride;
uint32_t output_scan_lines;
uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
uint32_t plane_addr_offset;
uint8_t csid_src; /*RDI 0-2*/
uint8_t rdi_cid;/*CID 1-16*/
};
enum msm_stream_memory_input_t {
MEMORY_INPUT_DISABLED,
MEMORY_INPUT_ENABLED
};
struct msm_vfe_axi_stream_request_cmd {
uint32_t session_id;
uint32_t stream_id;
uint32_t vt_enable;
uint32_t output_format;/*Planar/RAW/Misc*/
enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
uint32_t burst_count;
uint32_t hfr_mode;
uint8_t frame_base;
uint32_t init_frame_drop; /*MAX 31 Frames*/
enum msm_vfe_frame_skip_pattern frame_skip_pattern;
uint8_t buf_divert; /* if TRUE no vb2 buf done. */
/*Return values*/
uint32_t axi_stream_handle;
uint32_t controllable_output;
uint32_t burst_len;
/* Flag indicating memory input stream */
enum msm_stream_memory_input_t memory_input;
};
struct msm_vfe_axi_stream_release_cmd {
uint32_t stream_handle;
};
enum msm_vfe_axi_stream_cmd {
STOP_STREAM,
START_STREAM,
STOP_IMMEDIATELY,
};
struct msm_vfe_axi_stream_cfg_cmd {
uint8_t num_streams;
uint32_t stream_handle[VFE_AXI_SRC_MAX];
enum msm_vfe_axi_stream_cmd cmd;
uint8_t sync_frame_id_src;
};
enum msm_vfe_axi_stream_update_type {
ENABLE_STREAM_BUF_DIVERT,
DISABLE_STREAM_BUF_DIVERT,
UPDATE_STREAM_FRAMEDROP_PATTERN,
UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
UPDATE_STREAM_AXI_CONFIG,
UPDATE_STREAM_REQUEST_FRAMES,
UPDATE_STREAM_ADD_BUFQ,
UPDATE_STREAM_REMOVE_BUFQ,
UPDATE_STREAM_SW_FRAME_DROP,
};
enum msm_vfe_iommu_type {
IOMMU_ATTACH,
IOMMU_DETACH,
};
enum msm_vfe_buff_queue_id {
VFE_BUF_QUEUE_DEFAULT,
VFE_BUF_QUEUE_SHARED,
VFE_BUF_QUEUE_MAX,
};
struct msm_vfe_axi_stream_cfg_update_info {
uint32_t stream_handle;
uint32_t output_format;
uint32_t user_stream_id;
uint32_t frame_id;
enum msm_vfe_frame_skip_pattern skip_pattern;
struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
struct msm_isp_sw_framskip sw_skip_info;
};
struct msm_vfe_axi_halt_cmd {
uint32_t stop_camif;
uint32_t overflow_detected;
uint32_t blocking_halt;
};
struct msm_vfe_axi_reset_cmd {
uint32_t blocking;
uint32_t frame_id;
};
struct msm_vfe_axi_restart_cmd {
uint32_t enable_camif;
};
struct msm_vfe_axi_stream_update_cmd {
uint32_t num_streams;
enum msm_vfe_axi_stream_update_type update_type;
struct msm_vfe_axi_stream_cfg_update_info
update_info[MSM_ISP_STATS_MAX];
};
struct msm_vfe_smmu_attach_cmd {
uint32_t security_mode;
uint32_t iommu_attach_mode;
};
struct msm_vfe_stats_stream_request_cmd {
uint32_t session_id;
uint32_t stream_id;
enum msm_isp_stats_type stats_type;
uint32_t composite_flag;
uint32_t framedrop_pattern;
uint32_t init_frame_drop; /*MAX 31 Frames*/
uint32_t irq_subsample_pattern;
uint32_t buffer_offset;
uint32_t stream_handle;
};
struct msm_vfe_stats_stream_release_cmd {
uint32_t stream_handle;
};
struct msm_vfe_stats_stream_cfg_cmd {
uint8_t num_streams;
uint32_t stream_handle[MSM_ISP_STATS_MAX];
uint8_t enable;
uint32_t stats_burst_len;
};
enum msm_vfe_reg_cfg_type {
VFE_WRITE,
VFE_WRITE_MB,
VFE_READ,
VFE_CFG_MASK,
VFE_WRITE_DMI_16BIT,
VFE_WRITE_DMI_32BIT,
VFE_WRITE_DMI_64BIT,
VFE_READ_DMI_16BIT,
VFE_READ_DMI_32BIT,
VFE_READ_DMI_64BIT,
GET_MAX_CLK_RATE,
GET_CLK_RATES,
GET_ISP_ID,
VFE_HW_UPDATE_LOCK,
VFE_HW_UPDATE_UNLOCK,
SET_WM_UB_SIZE,
SET_UB_POLICY,
};
struct msm_vfe_cfg_cmd2 {
uint16_t num_cfg;
uint16_t cmd_len;
void __user *cfg_data;
void __user *cfg_cmd;
};
struct msm_vfe_cfg_cmd_list {
struct msm_vfe_cfg_cmd2 cfg_cmd;
struct msm_vfe_cfg_cmd_list *next;
uint32_t next_size;
};
struct msm_vfe_reg_rw_info {
uint32_t reg_offset;
uint32_t cmd_data_offset;
uint32_t len;
};
struct msm_vfe_reg_mask_info {
uint32_t reg_offset;
uint32_t mask;
uint32_t val;
};
struct msm_vfe_reg_dmi_info {
uint32_t hi_tbl_offset; /*Optional*/
uint32_t lo_tbl_offset; /*Required*/
uint32_t len;
};
struct msm_vfe_reg_cfg_cmd {
union {
struct msm_vfe_reg_rw_info rw_info;
struct msm_vfe_reg_mask_info mask_info;
struct msm_vfe_reg_dmi_info dmi_info;
} u;
enum msm_vfe_reg_cfg_type cmd_type;
};
enum vfe_sd_type {
VFE_SD_0 = 0,
VFE_SD_1,
VFE_SD_COMMON,
VFE_SD_MAX,
};
/* When you change the value below, check for the sof event_data size.
* V4l2 limits payload to 64 bytes */
#define MS_NUM_SLAVE_MAX 1
/* Usecases when 2 HW need to be related or synced */
enum msm_vfe_dual_hw_type {
DUAL_NONE = 0,
DUAL_HW_VFE_SPLIT = 1,
DUAL_HW_MASTER_SLAVE = 2,
};
/* Type for 2 INTF when used in Master-Slave mode */
enum msm_vfe_dual_hw_ms_type {
MS_TYPE_NONE,
MS_TYPE_MASTER,
MS_TYPE_SLAVE,
};
struct msm_isp_set_dual_hw_ms_cmd {
uint8_t num_src;
/* Each session can be only one type but multiple intf if YUV cam */
enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
/* Primary intf is mostly associated with preview.
* This primary intf SOF frame_id and timestamp is tracked
* and used to calculate delta */
enum msm_vfe_input_src primary_intf;
/* input_src array indicates other input INTF that may be Master/Slave.
* For these additional intf, frame_id and timestamp are not saved.
* However, if these are slaves then they will still get their
* frame_id from Master */
enum msm_vfe_input_src input_src[VFE_SRC_MAX];
uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */
};
enum msm_isp_buf_type {
ISP_PRIVATE_BUF,
ISP_SHARE_BUF,
MAX_ISP_BUF_TYPE,
};
struct msm_isp_unmap_buf_req {
uint32_t fd;
};
struct msm_isp_buf_request {
uint32_t session_id;
uint32_t stream_id;
uint8_t num_buf;
uint32_t handle;
enum msm_isp_buf_type buf_type;
};
struct msm_isp_qbuf_plane {
uint32_t addr;
uint32_t offset;
uint32_t length;
};
struct msm_isp_qbuf_buffer {
struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
uint32_t num_planes;
};
struct msm_isp_qbuf_info {
uint32_t handle;
int32_t buf_idx;
/*Only used for prepare buffer*/
struct msm_isp_qbuf_buffer buffer;
/*Only used for diverted buffer*/
uint32_t dirty_buf;
};
struct msm_isp_clk_rates {
uint32_t svs_rate;
uint32_t nominal_rate;
uint32_t high_rate;
};
struct msm_vfe_axi_src_state {
enum msm_vfe_input_src input_src;
uint32_t src_active;
uint32_t src_frame_id;
};
enum msm_isp_event_mask_index {
ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0,
ISP_EVENT_MASK_INDEX_ERROR = 1,
ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2,
ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3,
ISP_EVENT_MASK_INDEX_REG_UPDATE = 4,
ISP_EVENT_MASK_INDEX_SOF = 5,
ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6,
ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7,
ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8,
ISP_EVENT_MASK_INDEX_BUF_DONE = 9,
ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10,
ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11,
ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12,
};
#define ISP_EVENT_SUBS_MASK_NONE 0
#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
#define ISP_EVENT_SUBS_MASK_ERROR \
(1 << ISP_EVENT_MASK_INDEX_ERROR)
#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
#define ISP_EVENT_SUBS_MASK_REG_UPDATE \
(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
#define ISP_EVENT_SUBS_MASK_SOF \
(1 << ISP_EVENT_MASK_INDEX_SOF)
#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
#define ISP_EVENT_SUBS_MASK_BUF_DONE \
(1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \
(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \
(1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \
(1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
enum msm_isp_event_idx {
ISP_REG_UPDATE = 0,
ISP_EPOCH_0 = 1,
ISP_EPOCH_1 = 2,
ISP_START_ACK = 3,
ISP_STOP_ACK = 4,
ISP_IRQ_VIOLATION = 5,
ISP_STATS_OVERFLOW = 6,
ISP_BUF_DONE = 7,
ISP_FE_RD_DONE = 8,
ISP_IOMMU_P_FAULT = 9,
ISP_ERROR = 10,
ISP_HW_FATAL_ERROR = 11,
ISP_PING_PONG_MISMATCH = 12,
ISP_REG_UPDATE_MISSING = 13,
ISP_BUF_FATAL_ERROR = 14,
ISP_EVENT_MAX = 15
};
#define ISP_EVENT_OFFSET 8
#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0)
#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1)
#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR)
#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE)
#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1)
#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE)
#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE)
#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE)
/* The msm_v4l2_event_data structure should match the
* v4l2_event.u.data field.
* should not exceed 64 bytes */
struct msm_isp_buf_event {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
uint32_t output_format;
int8_t buf_idx;
};
struct msm_isp_fetch_eng_event {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
uint32_t fd;
int8_t buf_idx;
int8_t offline_mode;
};
struct msm_isp_stats_event {
uint32_t stats_mask; /* 4 bytes */
uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */
};
struct msm_isp_stream_ack {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
};
enum msm_vfe_error_type {
ISP_ERROR_NONE,
ISP_ERROR_CAMIF,
ISP_ERROR_BUS_OVERFLOW,
ISP_ERROR_RETURN_EMPTY_BUFFER,
ISP_ERROR_FRAME_ID_MISMATCH,
ISP_ERROR_MAX,
};
struct msm_isp_error_info {
enum msm_vfe_error_type err_type;
uint32_t session_id;
uint32_t stream_id;
uint32_t stream_id_mask;
};
/* This structure reports delta between master and slave */
struct msm_isp_ms_delta_info {
uint8_t num_delta_info;
uint32_t delta[MS_NUM_SLAVE_MAX];
};
/* This is sent in EPOCH irq */
struct msm_isp_output_info {
uint8_t regs_not_updated;
/* mask with bufq_handle for regs not updated or return empty */
uint16_t output_err_mask;
/* mask with stream_idx for get_buf failed */
uint8_t stream_framedrop_mask;
/* mask with stats stream_idx for get_buf failed */
uint16_t stats_framedrop_mask;
/* delta between master and slave */
};
/* This structure is piggybacked with SOF event */
struct msm_isp_sof_info {
uint8_t regs_not_updated;
/* mask with AXI_SRC for regs not updated */
uint16_t reg_update_fail_mask;
/* mask with bufq_handle for get_buf failed */
uint32_t stream_get_buf_fail_mask;
/* mask with stats stream_idx for get_buf failed */
uint16_t stats_get_buf_fail_mask;
/* delta between master and slave */
struct msm_isp_ms_delta_info ms_delta_info;
};
struct msm_isp_event_data {
/*Wall clock except for buffer divert events
*which use monotonic clock
*/
struct timeval timestamp;
/* Monotonic timestamp since bootup */
struct timeval mono_timestamp;
uint32_t frame_id;
union {
/* Sent for Stats_Done event */
struct msm_isp_stats_event stats;
/* Sent for Buf_Divert event */
struct msm_isp_buf_event buf_done;
/* Sent for offline fetch done event */
struct msm_isp_fetch_eng_event fetch_done;
/* Sent for Error_Event */
struct msm_isp_error_info error_info;
/*
* This struct needs to be removed once
* userspace switches to sof_info
*/
struct msm_isp_output_info output_info;
/* Sent for SOF event */
struct msm_isp_sof_info sof_info;
} u; /* union can have max 52 bytes */
};
#ifdef CONFIG_COMPAT
struct msm_isp_event_data32 {
struct compat_timeval timestamp;
struct compat_timeval mono_timestamp;
uint32_t frame_id;
union {
struct msm_isp_stats_event stats;
struct msm_isp_buf_event buf_done;
struct msm_isp_fetch_eng_event fetch_done;
struct msm_isp_error_info error_info;
struct msm_isp_output_info output_info;
struct msm_isp_sof_info sof_info;
} u;
};
#endif
#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
#define VIDIOC_MSM_VFE_REG_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
#define VIDIOC_MSM_ISP_REQUEST_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
#define VIDIOC_MSM_ISP_RELEASE_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
#define VIDIOC_MSM_ISP_REQUEST_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
#define VIDIOC_MSM_ISP_CFG_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
#define VIDIOC_MSM_ISP_RELEASE_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
#define VIDIOC_MSM_ISP_INPUT_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
#define VIDIOC_MSM_ISP_SET_SRC_STATE \
_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+9, \
struct msm_vfe_stats_stream_request_cmd)
#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+11, \
struct msm_vfe_stats_stream_release_cmd)
#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
_IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src)
#define VIDIOC_MSM_ISP_UPDATE_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
#define VIDIOC_MSM_VFE_REG_LIST_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list)
#define VIDIOC_MSM_ISP_SMMU_ATTACH \
_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd)
#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd)
#define VIDIOC_MSM_ISP_AXI_HALT \
_IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd)
#define VIDIOC_MSM_ISP_AXI_RESET \
_IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd)
#define VIDIOC_MSM_ISP_AXI_RESTART \
_IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd)
#define VIDIOC_MSM_ISP_FETCH_ENG_START \
_IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start)
#define VIDIOC_MSM_ISP_DEQUEUE_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+21, struct msm_isp_qbuf_info)
#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \
_IOWR('V', BASE_VIDIOC_PRIVATE+22, struct msm_isp_set_dual_hw_ms_cmd)
#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \
_IOWR('V', BASE_VIDIOC_PRIVATE+23, struct msm_vfe_fetch_eng_start)
#define VIDIOC_MSM_ISP_UNMAP_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+24, struct msm_isp_unmap_buf_req)
#endif /* __MSMB_ISP__ */

125
third_party/linux/include/msmb_ispif.h vendored Normal file
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@@ -0,0 +1,125 @@
#ifndef MSM_CAM_ISPIF_H
#define MSM_CAM_ISPIF_H
#define CSID_VERSION_V20 0x02000011
#define CSID_VERSION_V22 0x02001000
#define CSID_VERSION_V30 0x30000000
#define CSID_VERSION_V3 0x30000000
enum msm_ispif_vfe_intf {
VFE0,
VFE1,
VFE_MAX
};
#define VFE0_MASK (1 << VFE0)
#define VFE1_MASK (1 << VFE1)
enum msm_ispif_intftype {
PIX0,
RDI0,
PIX1,
RDI1,
RDI2,
INTF_MAX
};
#define MAX_PARAM_ENTRIES (INTF_MAX * 2)
#define MAX_CID_CH 8
#define PIX0_MASK (1 << PIX0)
#define PIX1_MASK (1 << PIX1)
#define RDI0_MASK (1 << RDI0)
#define RDI1_MASK (1 << RDI1)
#define RDI2_MASK (1 << RDI2)
enum msm_ispif_vc {
VC0,
VC1,
VC2,
VC3,
VC_MAX
};
enum msm_ispif_cid {
CID0,
CID1,
CID2,
CID3,
CID4,
CID5,
CID6,
CID7,
CID8,
CID9,
CID10,
CID11,
CID12,
CID13,
CID14,
CID15,
CID_MAX
};
enum msm_ispif_csid {
CSID0,
CSID1,
CSID2,
CSID3,
CSID_MAX
};
struct msm_ispif_params_entry {
enum msm_ispif_vfe_intf vfe_intf;
enum msm_ispif_intftype intftype;
int num_cids;
enum msm_ispif_cid cids[3];
enum msm_ispif_csid csid;
int crop_enable;
uint16_t crop_start_pixel;
uint16_t crop_end_pixel;
};
struct msm_ispif_param_data {
uint32_t num;
struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
};
struct msm_isp_info {
uint32_t max_resolution;
uint32_t id;
uint32_t ver;
};
struct msm_ispif_vfe_info {
int num_vfe;
struct msm_isp_info info[VFE_MAX];
};
enum ispif_cfg_type_t {
ISPIF_CLK_ENABLE,
ISPIF_CLK_DISABLE,
ISPIF_INIT,
ISPIF_CFG,
ISPIF_START_FRAME_BOUNDARY,
ISPIF_RESTART_FRAME_BOUNDARY,
ISPIF_STOP_FRAME_BOUNDARY,
ISPIF_STOP_IMMEDIATELY,
ISPIF_RELEASE,
ISPIF_ENABLE_REG_DUMP,
ISPIF_SET_VFE_INFO,
};
struct ispif_cfg_data {
enum ispif_cfg_type_t cfg_type;
union {
int reg_dump; /* ISPIF_ENABLE_REG_DUMP */
uint32_t csid_version; /* ISPIF_INIT */
struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */
struct msm_ispif_param_data params; /* CFG, START, STOP */
};
};
#define VIDIOC_MSM_ISPIF_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
#endif /* MSM_CAM_ISPIF_H */

1696
third_party/linux/include/v4l2-controls.h vendored Normal file
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