openpilot v0.9.6 release
date: 2024-01-12T10:13:37 master commit: ba792d576a49a0899b88a753fa1c52956bedf9e6
This commit is contained in:
FrogAi
69
body/board/drivers/angle_sensor.h
Normal file
69
body/board/drivers/angle_sensor.h
Normal file
@@ -0,0 +1,69 @@
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// Default addresses for AS5048B
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#define AS5048_ADDRESS_LEFT 0x40
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#define AS5048_ADDRESS_RIGHT 0x41
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#define UNKNOWN_IMU 0x68
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#define AS5048B_PROG_REG 0x03
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#define AS5048B_ADDR_REG 0x15
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#define AS5048B_ZEROMSB_REG 0x16 //bits 0..7
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#define AS5048B_ZEROLSB_REG 0x17 //bits 0..5
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#define AS5048B_GAIN_REG 0xFA
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#define AS5048B_DIAG_REG 0xFB
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#define AS5048B_MAGNMSB_REG 0xFC //bits 0..7
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#define AS5048B_MAGNLSB_REG 0xFD //bits 0..5
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#define AS5048B_ANGLMSB_REG 0xFE //bits 0..7
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#define AS5048B_ANGLLSB_REG 0xFF //bits 0..5
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extern I2C_HandleTypeDef hi2c1;
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const uint8_t init_imu_regaddr[] = {0x76, 0x4c, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53};
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const uint8_t init_imu_data[] = {0x00, 0x12, 0x2f, 0x26, 0x67, 0x04, 0x00, 0x00};
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fault_status_t fault_status = {0};
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void angle_sensor_read(uint16_t *sensor_angle) {
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if (fault_status.left_i2c && fault_status.right_i2c) { // Try to reinitialize halted I2C
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if (HAL_I2C_Init(&hi2c1) == HAL_OK) {
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fault_status.left_i2c = 0;
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fault_status.right_i2c = 0;
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}
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}
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uint8_t buf[2];
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if (HAL_I2C_Mem_Read(&hi2c1, (AS5048_ADDRESS_LEFT<<1), AS5048B_ANGLMSB_REG, I2C_MEMADD_SIZE_8BIT, buf, 2, 10) == HAL_OK) {
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sensor_angle[0] = (buf[0] << 6) | (buf[1] & 0x3F);
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fault_status.left_i2c = 0;
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} else {
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fault_status.left_i2c = 1;
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}
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if (HAL_I2C_Mem_Read(&hi2c1, (AS5048_ADDRESS_RIGHT<<1), AS5048B_ANGLMSB_REG, I2C_MEMADD_SIZE_8BIT, buf, 2, 10) == HAL_OK) {
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sensor_angle[1] = (buf[0] << 6) | (buf[1] & 0x3F);
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fault_status.right_i2c = 0;
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} else {
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fault_status.right_i2c = 1;
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}
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}
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void IMU_soft_init(void) {
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i2c_port_init();
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for (int8_t i = 3; i > 0; i--) {
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SW_I2C_WriteControl_8Bit((UNKNOWN_IMU<<1), 0x75, 0x00);
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}
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for (int8_t i = sizeof(init_imu_regaddr)-1; i >= 0; i--) {
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SW_I2C_WriteControl_8Bit((UNKNOWN_IMU<<1), init_imu_regaddr[i], init_imu_data[i]);
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}
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}
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void IMU_soft_sensor_read(uint16_t *unknown_imu_data) {
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static uint8_t buf[12];
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SW_I2C_WriteControl_8Bit((UNKNOWN_IMU<<1), 0x76, 0x00);
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SW_I2C_Multi_ReadnControl_8Bit((UNKNOWN_IMU<<1), 0x1F, 6, buf);
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SW_I2C_Multi_ReadnControl_8Bit((UNKNOWN_IMU<<1), 0x25, 6, &buf[6]);
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for (int8_t i = 5; i >= 0; i--) {
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unknown_imu_data[i] = (buf[i*2] << 8) | (buf[(i*2)+1]);
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}
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}
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63
body/board/drivers/clock.h
Normal file
63
body/board/drivers/clock.h
Normal file
@@ -0,0 +1,63 @@
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void Error_Handler(void)
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{
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/* USER CODE BEGIN Error_Handler_Debug */
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/* User can add his own implementation to report the HAL error return state */
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__disable_irq();
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while (1)
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{
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}
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/* USER CODE END Error_Handler_Debug */
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}
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/** System Clock Configuration
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*/
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void SystemClock_Config(void) {
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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/** Configure the main internal regulator output voltage
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*/
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 96; // Gives 96 Mhz core clock
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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Error_Handler();
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}
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/**Configure the Systick interrupt time
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*/
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
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/**Configure the Systick
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*/
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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/* SysTick_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
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}
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305
body/board/drivers/i2c_soft.h
Normal file
305
body/board/drivers/i2c_soft.h
Normal file
@@ -0,0 +1,305 @@
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#define SW_I2C_WAIT_TIME 22
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#define I2C_READ 0x01
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#define READ_CMD 1
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#define WRITE_CMD 0
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void SW_I2C_init(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure = { 0 };
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GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStructure.Pin = SW_I2C1_SCL_PIN;
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HAL_GPIO_Init(SW_I2C1_SCL_GPIO, &GPIO_InitStructure);
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GPIO_InitStructure.Pin = SW_I2C1_SDA_PIN;
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HAL_GPIO_Init(SW_I2C1_SDA_GPIO, &GPIO_InitStructure);
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}
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uint8_t SW_I2C_ReadVal_SDA(void)
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{
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uint8_t ret;
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ret = (uint16_t)HAL_GPIO_ReadPin(SW_I2C1_SDA_GPIO, SW_I2C1_SDA_PIN);
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return ret;
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}
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void sda_high(void)
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{
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HAL_GPIO_WritePin(SW_I2C1_SDA_GPIO, SW_I2C1_SDA_PIN, GPIO_PIN_SET);
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}
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void sda_low(void)
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{
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HAL_GPIO_WritePin(SW_I2C1_SDA_GPIO, SW_I2C1_SDA_PIN, GPIO_PIN_RESET);
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}
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void scl_high(void)
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{
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HAL_GPIO_WritePin(SW_I2C1_SCL_GPIO, SW_I2C1_SCL_PIN, GPIO_PIN_SET);
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}
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void scl_low(void)
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{
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HAL_GPIO_WritePin(SW_I2C1_SCL_GPIO, SW_I2C1_SCL_PIN, GPIO_PIN_RESET);
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}
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void sda_out(uint8_t out)
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{
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if (out) {
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sda_high();
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} else {
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sda_low();
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}
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}
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void sda_in_mode(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure = { 0 };
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GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
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GPIO_InitStructure.Pin = SW_I2C1_SDA_PIN;
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HAL_GPIO_Init(SW_I2C1_SDA_GPIO, &GPIO_InitStructure);
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}
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void sda_out_mode(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure = { 0 };
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GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_OD;
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GPIO_InitStructure.Pin = SW_I2C1_SDA_PIN;
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HAL_GPIO_Init(SW_I2C1_SDA_GPIO, &GPIO_InitStructure);
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}
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void i2c_clk_data_out(void)
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{
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scl_high();
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delay(SW_I2C_WAIT_TIME);
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scl_low();
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}
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void i2c_port_init(void)
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{
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sda_high();
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scl_high();
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}
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void i2c_start_condition(void)
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{
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sda_high();
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scl_high();
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delay(SW_I2C_WAIT_TIME);
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sda_low();
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delay(SW_I2C_WAIT_TIME);
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scl_low();
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delay(SW_I2C_WAIT_TIME << 1);
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}
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void i2c_stop_condition(void)
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{
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sda_low();
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scl_high();
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delay(SW_I2C_WAIT_TIME);
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sda_high();
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delay(SW_I2C_WAIT_TIME);
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}
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uint8_t i2c_check_ack(void)
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{
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uint8_t ack;
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int i;
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unsigned int temp;
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sda_in_mode();
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scl_high();
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ack = 0;
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delay(SW_I2C_WAIT_TIME);
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for (i = 10; i > 0; i--) {
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temp = !(SW_I2C_ReadVal_SDA());
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if (temp)
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{
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ack = 1;
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break;
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}
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}
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scl_low();
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sda_out_mode();
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delay(SW_I2C_WAIT_TIME);
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return ack;
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}
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void i2c_check_not_ack(void)
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{
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sda_in_mode();
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i2c_clk_data_out();
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sda_out_mode();
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delay(SW_I2C_WAIT_TIME);
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}
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void i2c_slave_address(uint8_t IICID, uint8_t readwrite)
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{
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int x;
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if (readwrite) {
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IICID |= I2C_READ;
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} else {
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IICID &= ~I2C_READ;
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}
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scl_low();
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for (x = 7; x >= 0; x--) {
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sda_out(IICID & (1 << x));
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delay(SW_I2C_WAIT_TIME);
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i2c_clk_data_out();
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}
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}
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void i2c_register_address(uint8_t addr)
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{
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int x;
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scl_low();
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for (x = 7; x >= 0; x--) {
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sda_out(addr & (1 << x));
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delay(SW_I2C_WAIT_TIME);
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i2c_clk_data_out();
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}
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}
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void i2c_send_ack(void)
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{
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sda_out_mode();
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sda_low();
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delay(SW_I2C_WAIT_TIME);
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scl_high();
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delay(SW_I2C_WAIT_TIME << 1);
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sda_low();
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||||
delay(SW_I2C_WAIT_TIME << 1);
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||||
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scl_low();
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||||
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sda_out_mode();
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||||
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delay(SW_I2C_WAIT_TIME);
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}
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||||
void SW_I2C_Write_Data(uint8_t data)
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||||
{
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int x;
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scl_low();
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||||
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||||
for (x = 7; x >= 0; x--) {
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sda_out(data & (1 << x));
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||||
delay(SW_I2C_WAIT_TIME);
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i2c_clk_data_out();
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||||
}
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||||
}
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uint8_t SW_I2C_Read_Data(void)
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{
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int x;
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uint8_t readdata = 0;
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sda_in_mode();
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||||
for (x = 8; x--;) {
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scl_high();
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||||
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||||
readdata <<= 1;
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if (SW_I2C_ReadVal_SDA()) { readdata |= 0x01; }
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||||
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||||
delay(SW_I2C_WAIT_TIME);
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||||
scl_low();
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||||
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||||
delay(SW_I2C_WAIT_TIME);
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||||
}
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||||
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sda_out_mode();
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||||
return readdata;
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||||
}
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||||
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||||
uint8_t SW_I2C_WriteControl_8Bit(uint8_t IICID, uint8_t regaddr, uint8_t data)
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{
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uint8_t returnack = true;
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||||
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i2c_start_condition();
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||||
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||||
i2c_slave_address(IICID, WRITE_CMD);
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||||
if (!i2c_check_ack()) { returnack = false; }
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||||
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||||
delay(SW_I2C_WAIT_TIME);
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||||
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||||
i2c_register_address(regaddr);
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||||
if (!i2c_check_ack()) { returnack = false; }
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||||
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||||
delay(SW_I2C_WAIT_TIME);
|
||||
|
||||
SW_I2C_Write_Data(data);
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||||
if (!i2c_check_ack()) { returnack = false; }
|
||||
|
||||
delay(SW_I2C_WAIT_TIME);
|
||||
|
||||
i2c_stop_condition();
|
||||
|
||||
return returnack;
|
||||
}
|
||||
|
||||
uint8_t SW_I2C_Multi_ReadnControl_8Bit(uint8_t IICID, uint8_t regaddr, uint8_t rcnt, uint8_t (*pdata))
|
||||
{
|
||||
uint8_t returnack = true;
|
||||
uint8_t index;
|
||||
|
||||
i2c_port_init();
|
||||
|
||||
i2c_start_condition();
|
||||
|
||||
i2c_slave_address(IICID, WRITE_CMD);
|
||||
if (!i2c_check_ack()) { returnack = false; }
|
||||
|
||||
delay(SW_I2C_WAIT_TIME);
|
||||
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||||
i2c_register_address(regaddr);
|
||||
if (!i2c_check_ack()) { returnack = false; }
|
||||
|
||||
delay(SW_I2C_WAIT_TIME);
|
||||
|
||||
i2c_start_condition();
|
||||
|
||||
i2c_slave_address(IICID, READ_CMD);
|
||||
if (!i2c_check_ack()) { returnack = false; }
|
||||
|
||||
for ( index = 0 ; index < (rcnt-1) ; index++) {
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||||
delay(SW_I2C_WAIT_TIME);
|
||||
pdata[index] = SW_I2C_Read_Data();
|
||||
i2c_send_ack();
|
||||
}
|
||||
|
||||
pdata[rcnt-1] = SW_I2C_Read_Data();
|
||||
|
||||
i2c_check_not_ack();
|
||||
|
||||
i2c_stop_condition();
|
||||
|
||||
return returnack;
|
||||
}
|
||||
125
body/board/drivers/llbxcan.h
Normal file
125
body/board/drivers/llbxcan.h
Normal file
@@ -0,0 +1,125 @@
|
||||
// SAE 2284-3 : minimum 16 tq, SJW 3, sample point at 81.3%
|
||||
#define CAN_QUANTA 16U
|
||||
#define CAN_SEQ1 12U
|
||||
#define CAN_SEQ2 3U
|
||||
#define CAN_SJW 3U
|
||||
|
||||
#define CAN_PCLK (CORE_FREQ / 2U / 1000U)
|
||||
#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))
|
||||
#define CAN_INIT_TIMEOUT_MS 500
|
||||
|
||||
bool llcan_set_speed(CAN_TypeDef *CAN_obj, uint32_t speed, bool loopback, bool silent) {
|
||||
bool ret = true;
|
||||
|
||||
// initialization mode
|
||||
CAN1->MCR = CAN_MCR_INRQ; // When we want to use only CAN2 - need to do that
|
||||
CAN_obj->MCR = CAN_MCR_INRQ;
|
||||
uint32_t timeout_counter = 0U;
|
||||
while((CAN_obj->MSR & CAN_MSR_INAK) != CAN_MSR_INAK){
|
||||
// Delay for about 1ms
|
||||
delay(10000);
|
||||
timeout_counter++;
|
||||
|
||||
if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(ret){
|
||||
// set time quanta from defines
|
||||
CAN_obj->BTR = ((CAN_BTR_TS1_0 * (CAN_SEQ1-1)) |
|
||||
(CAN_BTR_TS2_0 * (CAN_SEQ2-1)) |
|
||||
(CAN_BTR_SJW_0 * (CAN_SJW-1)) |
|
||||
(can_speed_to_prescaler(speed) - 1U));
|
||||
|
||||
// silent loopback mode for debugging
|
||||
if (loopback) {
|
||||
CAN_obj->BTR |= CAN_BTR_SILM | CAN_BTR_LBKM;
|
||||
}
|
||||
if (silent) {
|
||||
CAN_obj->BTR |= CAN_BTR_SILM;
|
||||
}
|
||||
|
||||
CAN_obj->MCR |= CAN_MCR_AWUM; // Automatic wakeup mode
|
||||
CAN_obj->MCR |= CAN_MCR_ABOM; // Automatic bus-off management
|
||||
CAN_obj->MCR &= ~CAN_MCR_NART; // Automatic retransmission
|
||||
CAN_obj->MCR |= CAN_MCR_TXFP; // Priority driven by the request order (chronologically)
|
||||
CAN_obj->MCR &= ~CAN_MCR_INRQ;
|
||||
|
||||
timeout_counter = 0U;
|
||||
while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {
|
||||
// Delay for about 1ms
|
||||
delay(10000);
|
||||
timeout_counter++;
|
||||
|
||||
if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool llcan_init(CAN_TypeDef *CAN_obj) {
|
||||
bool ret = true;
|
||||
|
||||
// Enter init mode
|
||||
CAN_obj->FMR |= CAN_FMR_FINIT;
|
||||
|
||||
// Wait for INAK bit to be set
|
||||
uint32_t timeout_counter = 0U;
|
||||
while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {
|
||||
// Delay for about 1ms
|
||||
delay(10000);
|
||||
timeout_counter++;
|
||||
|
||||
if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(ret){
|
||||
// no mask
|
||||
// For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters.
|
||||
// Filters MUST be set always through CAN1(Master) as CAN2/3 are Slave
|
||||
CAN1->sFilterRegister[0].FR1 = 0U;
|
||||
CAN1->sFilterRegister[0].FR2 = 0U;
|
||||
CAN1->sFilterRegister[14].FR1 = 0U;
|
||||
CAN1->sFilterRegister[14].FR2 = 0U;
|
||||
CAN1->FA1R |= 1U | (1U << 14);
|
||||
|
||||
// Exit init mode, do not wait
|
||||
CAN_obj->FMR &= ~CAN_FMR_FINIT;
|
||||
|
||||
// enable certain CAN interrupts
|
||||
CAN1->IER = 0U; // When we want to use only CAN2 - need to do that
|
||||
CAN_obj->IER = CAN_IER_FMPIE0 | CAN_IER_TMEIE | CAN_IER_WKUIE;
|
||||
|
||||
if (CAN_obj == CAN1) {
|
||||
HAL_NVIC_EnableIRQ(CAN1_TX_IRQn);
|
||||
HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
|
||||
HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
|
||||
} else {
|
||||
HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);
|
||||
HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
|
||||
HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void llcan_clear_send(CAN_TypeDef *CAN_obj) {
|
||||
CAN_obj->TSR |= CAN_TSR_ABRQ0;
|
||||
CAN_obj->MSR &= ~CAN_MSR_ERRI;
|
||||
// cppcheck-suppress selfAssignment ; needed to clear the register
|
||||
CAN_obj->MSR = CAN_obj->MSR;
|
||||
}
|
||||
26
body/board/drivers/llflash.h
Normal file
26
body/board/drivers/llflash.h
Normal file
@@ -0,0 +1,26 @@
|
||||
bool flash_is_locked(void) {
|
||||
return (FLASH->CR & FLASH_CR_LOCK);
|
||||
}
|
||||
|
||||
void flash_unlock(void) {
|
||||
FLASH->KEYR = 0x45670123;
|
||||
FLASH->KEYR = 0xCDEF89AB;
|
||||
}
|
||||
|
||||
bool flash_erase_sector(uint8_t sector, bool unlocked) {
|
||||
// don't erase the bootloader(sector 0)
|
||||
if (sector != 0 && sector < 12 && unlocked) {
|
||||
FLASH->CR = (sector << 3) | FLASH_CR_SER;
|
||||
FLASH->CR |= FLASH_CR_STRT;
|
||||
while (FLASH->SR & FLASH_SR_BSY);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void flash_write_word(void *prog_ptr, uint32_t data) {
|
||||
uint32_t *pp = prog_ptr;
|
||||
FLASH->CR = FLASH_CR_PSIZE_1 | FLASH_CR_PG;
|
||||
*pp = data;
|
||||
while (FLASH->SR & FLASH_SR_BSY);
|
||||
}
|
||||
Reference in New Issue
Block a user