openpilot v0.9.6 release
date: 2024-01-12T10:13:37 master commit: ba792d576a49a0899b88a753fa1c52956bedf9e6
This commit is contained in:
63
body/board/drivers/clock.h
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63
body/board/drivers/clock.h
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void Error_Handler(void)
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{
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/* USER CODE BEGIN Error_Handler_Debug */
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/* User can add his own implementation to report the HAL error return state */
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__disable_irq();
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while (1)
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{
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}
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/* USER CODE END Error_Handler_Debug */
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}
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/** System Clock Configuration
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*/
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void SystemClock_Config(void) {
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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/** Configure the main internal regulator output voltage
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*/
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 96; // Gives 96 Mhz core clock
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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Error_Handler();
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}
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/**Configure the Systick interrupt time
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*/
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
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/**Configure the Systick
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*/
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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/* SysTick_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
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}
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